Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
1998-12-07
2002-12-17
Talbot, Brian K. (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S098300, C427S125000, C438S626000, C438S627000, C438S643000, C438S645000, C438S653000, C438S672000, C438S675000, C438S686000, C438S687000
Reexamination Certificate
active
06495200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the electroless depositing of Copper plating for semiconductor devices and particularly to a method for forming a seeding layer for Cu electroless plating for a semiconductor device and more particularly to a method for forming a Pd/Pd acetate seeding layer for a Cu plug for a interconnect.
2. Description of the Prior Art
With continual decrease in semiconductor device dimensions and rapid increase in packing density, parallel development of multilayer interconnect technology cannot be overemphasized. Related issues like RC delay, cross talk, etc. become more important as the dimensions constantly scaled down to the deep submicron regime. Thus, advanced metalization materials are required. Copper has been very much envisioned to be the next potential candidate and deposition by the electroless approach appears to be an attractive one based on factors like low cost of ownership, complete via interconnect fill, etc. In general a catalytic seeding layer like CVD Cu or Pd/Pt deposited on a diffusion barrier like TiN and TaN is required. However, such process are either too costly or contain counterions.
U.S. Pat. No. 5,674,787 (Zhao )Selective electroless copper deposited interconnect plugs for ULSI applications—shows a selective Cu electroless deposition in a via hole using a seed layer. A contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. An electroless copper deposition technique is then used to auto-catalytically deposit copper in the via.
U.S. Pat. No. 4,574,095 (Baum): Selective deposition of copper—teaches a process for selectively depositing copper by first selectively depositing palladium seeds by irradiating a palladium compound with light. Following the deposition of the palladium seeds, copper is deposited by an electroless process.
U.S. Pat. No. 4,282,271 (Feldstein) shows another method of electroless depositing Cu.
However, an improved method of Cu electroless is needed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for using a palladium (Pd) acetate seed layer (with optional thermal decomposition) for electroless copper plating.
It is an object of the present invention to provide a method for using a Pd acetate seed layer (with/with out optional thermal decomposition) for electroless copper plating to form interconnect structures in semiconductor chip.
It is an objective of the present invention to provide a method to thermally treat Pd acetate (e.g., Pd metal) to form a seeding layer.
It is yet another objective of the present invention to form a Pd passivation cap layer over a Cu plug to minimize the oxidation of the Cu plug.
To accomplish the above objectives, the present invention provides a method to deposit a seeding layer for electroless copper plating to form an interconnect or conductive line. The invention has two preferred embodiments. The first embodiment forms an important seed layer
13
composed of Pd acetate by a spin-on or dip process for the electroless plating of a Cu fill
16
. See
FIGS. 1A-1D
.
The second embodiment forms a Pd passivation layer cap
17
B over the Cu fill
16
to prevent the Cu fill from oxidizing. See
FIGS. 2A
to
2
C and FIG.
3
.
The method for the first embodiment involves the following steps:
a) An insulating layer
11
having an opening
14
is formed over a substrate
10
; the insulating layer
11
having a top surface
11
A.
b) A diffusion barrier layer
12
is formed over the insulating layer
11
.
c) In a key step, a seeding film
13
composed of a combination of Palladium (Pd) and palladium acetate is formed over the diffusing barrier layer
12
. The seeding film
13
is formed by dip coating or spin-on.
d) In an optional thermal decomposition step, the seeding film
13
is thermally decomposed to change the Pd acetate into Palladium or a combination of Pd acetate and Pd.
e) Next, we chemical-mechanical polish and remove the seeding film
13
and the diffusing barrier layer
12
from over the top surface
11
A of the insulating layer
11
.
f) Now, we electrolessly plate Cu over the seeding film
13
forming a copper fill
16
(plug) filling the hole
14
.
g) The copper fill
16
is chemical-mechanical polished to planarize the copper fill (copper plug)
16
to a level even with the top surface
11
A of the insulating layer
11
.
The second embodiment forms a Pd passivation cap
17
B over the Cu fill
16
by a process involving the same steps as the first embodiment up to the electroless Plating of Cu. See
FIGS. 2A-2C
. The Second embodiment's Cu fill
16
only partially fills the hole
14
. Next, a key passivation layer composed of a combination of Pd/Pd acetate is formed on the Cu plug and at least fills the hole. The passivation layer is formed by a process of dip coating or spin-on. The passivation layer is then chemical-mechanical polished.
The invention's first embodiment application of thermal
on-thermal treated Pd acetate film
13
as a catalytic/seeding layer for electroless copper plating has several advantages:
the kinetics/rate of plating is either comparable or faster than that of the conventional approaches.
In the seed bath, undesirable counter ions like Cl
−
may be excluded with the present invention where by no such species is present.
The seeding bath comprises mainly two components: {circle around (
1
)} Pd acetate and {circle around (
2
)} a suitable solvent, unlike conventional seed baths whereby three or four toxic and corrosive components are required.
The present invention has lower cost of ownership.
The second embodiment of the present invention forms a Pd cap passivation layer
17
B over the Cu fill
16
. The Pd cap passivation layer
17
B prevents the Cu fill
16
from oxidizing.
REFERENCES:
patent: 4282271 (1981-08-01), Feldstein
patent: 4574095 (1986-03-01), Baum et al.
patent: 5153023 (1992-10-01), Orlowski et al.
patent: 5198389 (1993-03-01), Van Der Putten et al.
patent: 5656542 (1997-08-01), Miyata et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5834366 (1998-11-01), Akram
patent: 5891804 (1999-04-01), Havermann et al.
patent: 5895261 (1999-04-01), Schinella et al.
Chan Lap
Li Fong Yau
Ng Hou Tee
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Stoffel William J.
Talbot Brian K.
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