Method to combine zero-etch and STI-etch processes into one...

Details Method to combine zero-etch and STI-etch processes into one... Method to combine zero-etch and STI-etch processes into one...

2002-01-03

2003-12-23

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S401000, C438S427000

Reexamination Certificate

active

06667222

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming both alignment marks and shallow trench isolation (STI) in one process in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the manufacture of integrated circuits, layers of various materials are grown or deposited on underlying layers. Many of these layers are patterned using lithographic processes. In order for the completed integrated circuit to operate properly, the patterned layers must be aligned precisely with one another. One lithographic technique that is common in the art is the use of a stepper to image portions of a wafer progressively until the entire wafer has been processed. Alignment marks are formed on the wafer and used by the stepper to align the mask properly with previous layers.
The formation of alignment marks within the semiconductor substrate is called the zero-etch process. In this process, typically, an oxide layer is grown over the surface of the semiconductor substrate. A photoresist layer is patterned to leave an opening for an alignment mark. The oxide layer and the semiconductor substrate are etched within the opening to a depth of about 1200 Angstroms. The mask and oxide are removed to complete formation of the alignment mark.
Shallow trench isolation (STI) is often used in the fabrication of integrated circuits to separate active areas from one another. In the STI-etch process, a pad oxide layer is grown over the semiconductor substrate a silicon nitride layer is typically deposited over the pad oxide layer. A photoresist layer is patterned to leave an opening for a STI trench. The nitride layer, pad oxide layer, and the semiconductor substrate are etched within the opening to a depth of about 3500 Angstroms. The trench is filled with an insulating layer and planarized. The nitride and pad oxide layers are removed to complete formation of the STI. It is desired to integrate the zero-etch and STI-etch processes into one process in order to save process steps.
U.S. Pat. No. 5,786,260 and 6,049,137 to Jang et al and U.S. Pat. No. 6,043,133 to Jang et al disclose the formation of alignment marks, followed by deposition of pad oxide and silicon nitride layers, and then simultaneous formation of STI trenches and trenches at the periphery of the alignment mark area. U.S. Pat. No. 5,950,093 to Wei teaches first forming an alignment mark, then etching an STI trench and extending the alignment mark trench to make it deeper than the STI trench. U.S. Pat. No. 5,893,744 to Wang etches STI trenches and alignment mark trenches sequentially and then fills both trenches in one step. U.S. Pat. No. 5,536,675 to Bohr teaches etching both shallow and deep trenches where a mask opening over the deep trench allow it to be etched deeper without etching into the shallow trench. None of these references combines the zero-etch and STI-etch processes into one process without adding masking or other steps.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for integrating the zero-etch and STI-etch processes into one process in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming an alignment mark and shallow trench isolation simultaneously.
In accordance with the objects of the invention, a method for integrating the zero-etch and STI-etch processes into one process is achieved. An etch stop layer is provided on a semiconductor substrate. A mask is formed overlying the etch stop layer having a first opening for a planned alignment mark and having a second opening for a planned shallow trench isolation region. The etch stop layer is etched away within the first and second openings and the semiconductor substrate exposed within the first and second openings is etched into a first depth to form a first trench underlying the first opening and a second trench underlying the second opening. The first trench is covered and the second trench is etched into the semiconductor substrate to a second depth greater than the first depth. The second trench is filled to complete formation of a shallow trench isolation region wherein the first trench completes formation of an alignment mark in the fabrication of an integrated circuit device.


REFERENCES:
patent: 5270265 (1993-12-01), Hemmenway et al.
patent: 5536675 (1996-07-01), Bohr
patent: 5646063 (1997-07-01), Mehta et al.
patent: 5786260 (1998-07-01), Jang et al.
patent: 5893744 (1999-04-01), Wang
patent: 5950093 (1999-09-01), Wei
patent: 6015744 (2000-01-01), Tseng
patent: 6043133 (2000-03-01), Jang et al.
patent: 6049137 (2000-04-01), Jang et al.
patent: 6440816 (2002-08-01), Farrow et al.
patent: 6444573 (2002-09-01), Wang et al.
patent: 6461937 (2002-10-01), Kim et al.

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