Patent
1996-04-18
1999-09-07
Teska, Kevin J.
G06F 9455
Patent
active
059499834
ABSTRACT:
One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.
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Fiuc Dan
Harms Jeanette S.
Richardson Kent
Teska Kevin J.
Xilinx , Inc.
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