Method to avoid copper contamination during copper etching...

Details Method to avoid copper contamination during copper etching... Method to avoid copper contamination during copper etching...

1999-11-19

2001-08-14

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S699000, C438S720000

Reexamination Certificate

active

06274499

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of avoiding contamination in copper metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
Copper metallization has become a future trend in integrated circuit manufacturing. However, copper contamination of the intermetal dielectric layer is a problem. Copper is a very dangerous contaminant and diffuses very quickly into silicon oxide, the most common material for interlevel dielectric (ILD) and intermetal dielectric (IMD). The application of a barrier layer underlying copper has effectively prevented the copper from making contact to the ILD or IMD layers during metallization. However, exposure of the IMD and ILD layers to copper during etching, chemical mechanical polishing (CMP), cleaning, and other processes is inevitable. This poses a threat for copper contamination control.
For example, when a copper layer
24
and barrier layer
22
over an oxide layer
14
are patterned, as shown in
FIG. 1
, copper ions
25
will penetrate the oxide layer
14
. Likewise, when a damascene or dual damascene process is used, as shown in
FIG. 2
, the copper
26
is typically polished using chemical mechanical polishing (CMP). Some of the copper may “smear”
27
onto the oxide
14
causing contamination. It is desired to prevent copper contamination during processing, including etching and CMP.
A number of patents address the damascene process. U.S. Pat. No. 5,451,551 to Krishnan et al teaches a method of forming a titanium tungsten cap over copper and polishing away the excess capping layer. U.S. Pat. No. 5,470,789 to Misawa shows a titanium nitride layer that is buff-abraded. U.S. Pat. No. 5,693,563 to Teong shows a barrier layer for copper, but the copper metallization is not recessed. U.S. Pat. No. 5,744,376 to Chan et al discloses a capping layer over a non-recessed copper metallization. U.S. Pat. No. 5,818,110 to Cronin shows a damascene process with an etch stop layer over metal plugs.
Other patents teach etching of metal layers. U.S. Pat. No. 5,766,974 to Sardella et al shows a SiON etch stop layer under a metal layer. U.S. Pat. No. 5,578,166 to Hirota teaches a refractory metal barrier in copper etching, but no barrier over the oxide layer. U.S. Pat. No. 5,240,559 to Ishida, U.S. Pat. No. 5,200,032 to Shinohara and U.S. Pat. No. 5,591,302 to Shinohara et al teach various RIE methods for copper, but without barrier layers over the oxide. U.S. Pat. No. 5,827,426 to Kamide et al disclose a 2-step etching of aluminum lines. U.S. Pat. No. 5,783,483 to Gardner teaches a metal oxide etch barrier under a metal layer. Gardner's barrier has a high dielectric constant and nonuniformity problems.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of copper metallization in the fabrication of integrated circuit devices.
Another object of the invention is to prevent copper contamination of the intermetal dielectric layer during etching of a copper line.
Yet another object of the invention is to prevent copper contamination of the intermetal dielectric layer during chemical mechanical polishing in a dual damascene process.
A further object of the invention is to prevent copper contamination of the intermetal dielectric layer during copper etching by forming a dielectric cap for isolation of the underlying dielectric layer.
A still further object of the invention is to prevent copper contamination of the intermetal dielectric layer during chemical mechanical polishing of copper by forming a dielectric cap for isolation of the underlying dielectric layer.
Yet another object of the invention is to prevent copper contamination of the intermetal dielectric layer during etching, chemical mechanical polishing, or cleaning of copper by forming a dielectric cap for isolation of the underlying dielectric layer.
In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is achieved. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via or contact opening is made through the dielectric cap layer and the dielectric layer and filled with a metal layer and planarized. A copper layer is deposited overlying the dielectric cap layer and planarized metal layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching.
In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A barrier metal layer is deposited overlying the dielectric cap layer and within the dual damascene opening. A copper layer is deposited overlying the barrier metal layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening wherein the dielectric cap layer prevents copper contamination of the dielectric layer during polishing.
Also, in accordance with the objects of the invention in the second embodiment, the copper layer is etched to form a recess within the dual damascene opening. A second dielectric cap layer is deposited overlying the barrier metal layer and the copper within the recess. The first and second dielectric cap layers and the barrier layer are removed except over the copper within the recess wherein the second dielectric cap layer prevents copper contamination in the fabrication of an integrated circuit device.


REFERENCES:
patent: 5200032 (1993-04-01), Shinohara
patent: 5240559 (1993-08-01), Ishida
patent: 5451551 (1995-09-01), Krishnan et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5578166 (1996-11-01), Hirota
patent: 5591302 (1997-01-01), Shinohara et al.
patent: 5693563 (1997-12-01), Teong
patent: 5744376 (1998-04-01), Chan et al.
patent: 5766974 (1998-06-01), Sardella et al.
patent: 5783483 (1998-07-01), Gardner
patent: 5818110 (1998-10-01), Cronin
patent: 5827436 (1998-10-01), Kamide et al.
patent: 6114242 (2000-09-01), Gupta et al.

Affiliated with

Also associated with

Rating

Method to avoid copper contamination during copper etching... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to avoid copper contamination during copper etching..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to avoid copper contamination during copper etching... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2522349