Method to avoid a laser marked area step height

Details Method to avoid a laser marked area step height Method to avoid a laser marked area step height

2007-02-06

2007-02-06

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S427000, C438S975000, C257S797000, C257SE21002

Reexamination Certificate

active

10761657

ABSTRACT:
A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

REFERENCES:
patent: 5911110 (1999-06-01), Yu
patent: 6215197 (2001-04-01), Iwamatsu
patent: 6603162 (2003-08-01), Uchiyama et al.
patent: 6667221 (2003-12-01), Kitazawa et al.
patent: 6790742 (2004-09-01), Yang et al.
patent: 6803291 (2004-10-01), Fu et al.

Affiliated with

Also associated with

Rating

Method to avoid a laser marked area step height does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to avoid a laser marked area step height, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to avoid a laser marked area step height will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3849041