Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-03-12
2002-06-11
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S079000, C216S088000, C216S099000, C438S723000, C438S745000, C438S756000, C438S757000
Reexamination Certificate
active
06403484
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming planarized shallow trench isolation structures in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is now commonly used in the art as an alternative to local oxidation of silicon (LOCOS) for forming isolations between active device areas in the integrated circuit. STI offers the advantages of smaller isolation area and better surface planarization when compared to LOCOS. However, the STI process suffers from dishing, especially over large trenches. Dishing can cause excessive device leakage in some cases. Currently, reverse masking and dummy active structures are the most commonly employed methods to prevent dishing during the STI chemical mechanical polishing (CMP) process. However, reverse masking steps incur additional processing costs. Dummy structures, on the other hand, cause an increase in parasitic capacitance that is not favorable, especially in mixed signal processes.
Co-pending U.S. patent application Ser. No. 09/439,357 (CS-99-059) to James Lee, filed on Nov. 15, 1999, teaches a new technique for preventing dishing in an STI process. This process requires an additional HF dip step. Several prior art approaches disclose methods to form and planarize shallow trench isolations. U.S. Pat. No. 6,057,210 to Yang et al shows a process in which corners of the silicon nitride areas are exposed using a wet etch. U.S. Pat. No. 5,441,094 to Pasch shows an STI process. U.S. Pat. No. 5,665,202 to Subramanian et al discloses an STI process in which varying pad pressure controls polish selectivity in the chemical mechanical polish (CMP) operation. U.S. Pat. No. 5,817,567 to Jang et al teaches a STI process in which a CMP process removes a silicon nitride layer and underlying oxide peaks. A single etch is used to remove both the remaining silicon nitride and a portion of the oxide. A second CMP is used to polish down the oxide to the top surface of the trench edges. U.S. Pat. No. 5,173,439 to Dash et al teaches another STI process using a polysilicon layer to shield the oxide in wide trenches. U.S. Pat. No. 5,880,007 to Varian et al teaches a polysilicon layer over HDP oxide within trenches. CMP exposes the oxide, then the polysilicon and oxide are etched separately followed by an oxide CMP. U.S. Pat. No. 5,792,707 to Chung teaches a reverse mask process. U.S. Pat. No. 5,498,565 to Gocho et al discloses several STI processes. U.S. Pat. No. 5,721,173 to Yano et al, U.S. Pat. No. 6,057,207 to Lin et al, U.S. Pat. No. 6,048,775 to Yao et al, and U.S. Pat. No. 5,721,172 to Jang et al show other related STI processes.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate shallow trench isolations where oxide dishing is eliminated.
Another object of the present invention is to provide a method to fabricate shallow trench isolations where the final thickness of the trench oxide is better controlled.
Yet another object of the invention is to provide a method to fabricate shallow trench isolations wherein oxide dishing is eliminated and the final thickness of the trench oxide is better controlled and wherein processing steps are minimized.
In accordance with the objects of this invention, a new method of forming shallow trench isolations has been achieved. A first etch stop layer is deposited on the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the first etch stop layer into the semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed wherein the second etch stop layer protects the oxide layer within the isolation trenches during the removing. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
REFERENCES:
patent: 5173439 (1992-12-01), Dash et al.
patent: 5441094 (1995-08-01), Pasch
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5721172 (1998-02-01), Jang et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5792707 (1998-08-01), Chung
patent: 5817567 (1998-10-01), Jang et al.
patent: 5880007 (1999-03-01), Varian et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6057207 (2000-05-01), Lin et al.
patent: 6057210 (2000-05-01), Yang et al.
Chan Lap
Feng Chen
Goh Wang Ling
Lee James
Lim Victor Seng Keong
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L.S.
Powell William A.
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