Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2002-04-15
2003-09-09
Barr, Michael (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S304000, C427S305000, C427S405000, C427S437000, C427S438000, C427S443100
Reexamination Certificate
active
06616967
ABSTRACT:
FIELD OF INVENTION
This invention relates to electroless nickel plating process and more particularly to a method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating processes.
BACKGROUND OF INVENTION
In integrated circuits (IC) technology, pure or doped aluminum has been the metallization of choice for interconnection and bond pads. The main advantages of aluminum include easy deposition and patterning. Further, the technology of bonding wires made of gold, copper, or aluminum to the aluminum bond pads has developed to a high level of automation, miniaturization, and reliability.
In the continuing trend to miniaturize the ICs, the RC time constant of the interconnection between active circuit elements increasingly dominates the achievable IC speed-power product. Consequently, the relatively high resistivity of the interconnecting aluminum appears inferior to the lower resistivity of metals such as copper. Further, the pronounced sensitivity of aluminum to electromigration is becoming a serious obstacle to increased miniaturization. Consequently, there is now a strong drive in the semiconductor industry to employ copper as the preferred interconnecting metal, based on its higher electrical conductivity and lower electromigration sensitivity. From the standpoint of the mature aluminum interconnection technology, however, this shift to copper is a significant technological challenge.
Copper has to be shielded from diffusing into the silicon base material of the ICs in order to protect the circuits from the carrier lifetime killing characteristic of copper atoms positioned in the silicon lattice. For bond pads made of copper, the formation of thin copper (I) oxide films during the manufacturing process flow has to be prevented since these films severely inhibit reliable attachment of bonding wires, especially for conventional gold-wire thermosonic ball bonding. In contrast to aluminum oxide films overlying metallic aluminum, copper oxide films overlying metallic copper cannot easily be broken by a combination of thermocompression and ultrasonic energy applied in the bonding process. This means that the bond pad has to be cleaned to remove oxides immediately prior to bonding. This involves an additional process step and still carries the risk of too much time elapsing between cleaning and bonding in which case the bond may fail. As a further difficulty, bare copper bond pads are susceptible to corrosion. Copper oxide continues to grow with time. It is possible to bond through thin copper oxide.
Oxidation of aluminium, however, is self-limiting. That is after a mono-layer of aluminium oxide forms, no further oxidation occurs. It is possible to bond through this oxide.
In order to overcome these problems, a process has been disclosed to cap the clean copper bond pad with a layer of aluminum and thus re-construct the traditional situation of an aluminum pad to be bonded by conventional gold-wire ball bonding. A suitable bonding process is described in U.S. Pat. No. 5,785,236, issued on Jul. 28, 1998 (Cheung et al., “Advanced Copper Interconnect System that is Compatible with Existing IC Wire Bonding Technology”). The described approach, however, has several shortcomings.
First, the fabrication cost of the aluminum cap is higher than desired, since the process requires additional steps for depositing metal, patterning, etching, and cleaning. Second, the cap must be thick enough to prevent copper from diffusing through the cap metal and possibly poisoning the IC transistors. Third, there is a required barrier of TaN between the copper and aluminium to prevent migration. Fourth, the aluminum used for the cap is soft and thus gets severely damaged by the markings of the multiprobe contacts in electrical testing. This damnage, in turn, becomes so dominant in the ever decreasing size of the bond pads that the subsequent ball bond attachment is no longer reliable.
A low-cost structure and method for capping the copper bond pads of copper-metallized ICs has been disclosed by Roger J. Stierman et al in U.S. patent application Ser. No. 09/775,322, filed on Feb. 18, 2001 entitled Structure and Method for Bond Pads of Copper Metallization. This application is incorporated herein by reference. An urgent need has arisen for a reliable method of bonding wires to capped bond pads which combines minimum fabrication cost with maximum up-diffusion control of metals potentially capable of impending subsequent wire bonding. A robust, reliable and low cost metal structure and process enabling electrical wire connections to the interconnecting copper metallization of integrated circuits is described in application Ser. No. 09/817,696 filed Mar. 23, 2001 and is entitled “Wire Bonding Process For Copper-Metallized Integrated Circuits” filed by Howard Test; Gonzalo Amador; and Willmar Subido. This application is incorporated herein by reference. The structure comprises a layer of barrier metal that resists copper diffusion in a thickness such that the barrier layer reduces the diffusion of copper at 250 degrees C. by more than 80% compared with the absence of barrier metal. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and silver. The electroless process for fabricating the bond pad cap is illustrated in FIG.
2
. The bond pads are opened in the protective overcoat by a process that takes place toward the end of the wafer fabrication that occurs in the wafer fab. This exposes the copper IC metallization in bond pad areas, the cap deposition process starts at
101
; the sequence of process steps is as follows:
Step
102
: Is an optional step of coating the backside of the silicon IC wafer with resist using a spin-on technique. This coat will prevent unwanted metal deposition on the wafer backside. This may not be necessary if the back side has SiO2 on it.
Step
103
: Is an optional step of baking the resist, typically at 110 Degree C. for a time period of about 30 to 60 minutes.
Step
104
: Is an optional step of cleaning of the exposed bond pad copper surface using a plasma ashing process for about 2 minutes. This need not be used by limiting the time when the wafer is completed in the wafer fab and plating.
Step
105
: Cleaning by immersing the wafer, having the exposed copper of the bond pads, in a solution of sulfuric acid, nitric acids, or any other acid, for about 30 to 90 seconds. This is a cleaning process that removes organic contaminants from the surface of the bond pad and activates the surface with an acid etch using dilute acids.
Step
106
: Rinsing in a dump rinse station for about 60 to 180 seconds.
Step
107
: Immersing the wafer in a catalytic metal chloride solution, such as palladium chloride, for about 60 to 180 seconds “activates” the copper surface, i.e., a thin layer of seed metal (such as palladium) is deposited onto the clean, non-oxidized copper surface.
Step
108
: Rinsing in a dump rinse station for about 60 to 180 seconds.
Step
109
: Electroless plating of barrier metal against copper up-diffusion.
If nickel is selected, plating between 60 to 180 seconds will deposit about 0.2 to 0.6 &mgr;m thick nickel. Other thickness barrier may be used depending on the application.
Step
110
: Rinsing in a dump rinse station for about 60 to 180 seconds.
Step
111
: Electroless plating of outermost layer, which is bondable and simultaneously provides a barrier against up-diffusion of the underlying barrier metal. If gold or palladium is selected, plating between 10 to 20 minutes will deposit about 0.1 to 0.2 um of palladium and 40 to 80 nm Au, respectively. The palladium process is an electroless process that plates at the rate of about 0.01 um per minute. The gold process is an immersion process that is self limiting at about 0.08 um at 8 to 12 minutes. A preferred process uses first an electroless palladium process for between 8 and 22 minutes to deposit 0.1 and 0.3 &mgr;m of palladium followed by an immersion gold plating process step with self-limiting surface metal replacement. If gold
Barr Michael
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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