Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-06-28
2011-06-28
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S111000, C716S136000, C703S016000
Reexamination Certificate
active
07971166
ABSTRACT:
Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
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Seigler Adrian E.
Van Huben Gary A.
Campbell John E.
International Business Machines - Corporation
Jones II Graham S.
Kik Phallaka
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