Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Computer or peripheral device
Reexamination Certificate
2011-08-09
2011-08-09
Shah, Kamini S (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Computer or peripheral device
C711S214000, C711S217000, C711S218000, C712S205000, C712S206000, C712S207000
Reexamination Certificate
active
07996203
ABSTRACT:
A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.
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Bair Dean G.
Krygowski Christopher A.
Shum Chung-Lung K.
Xiao Wei-Yi
Alhija Saif A
Campbell John
Cantor & Colburn LLP
International Business Machines - Corporation
Shah Kamini S
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