Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-05-24
2011-05-24
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
Reexamination Certificate
active
07949972
ABSTRACT:
Systems, methods and computer program products for exploiting orthogonal control vectors in timing driven systems. An exemplary embodiment includes running an initial logic synthesis run on the system, identifying critical inputs to a logic cone related to the run, identifying orthogonal vectors in the logic cone, adding vectors to the logic cone, obtaining logical solutions and selecting a solution from the logical solutions.
REFERENCES:
patent: 7275224 (2007-09-01), Meaney et al.
patent: 7290240 (2007-10-01), Lam-Leventis et al.
Stok, L. et al., “Booledozer: Logic synthesis for ASICs”, Feb. 6, 1996, pp. 1-68.
Dave Allen, “Automatic one-hot-re-encoding for FPGAs”, Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping, ISBN 978-3-540-57091-2, pp. 71-77.
Busaba Fadi Y.
Hutton David S.
Krygowski Christopher A.
Malley Edward T.
Plate Jeffrey S.
Campbell John
Cantor & Colburn LLP
International Business Machines - Corporation
Whitmore Stacy A
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