Method, system and computer program product for efficiently...

Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors

Reexamination Certificate

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Details

C712S245000

Reexamination Certificate

active

07098921

ABSTRACT:
A memory management system provides microcode instructions that are divided into multiple tuned phases and stored as separate modules inside a phase code depository. A microcode manager, containing a mode detector, sequence identifier, code loader, drawing data processor and phase executor, interacts with a microcode processor and the phase code depository. The mode detector evaluates a user request for a desired mode. In response to a command from the mode detector, the sequence identifier selects a correct phase sequence that is needed to implement the desired mode. The code loader transfers the phase sequence from the phase code depository to the microcode processor where it is stored in a microcode instruction memory. The memory address for each module within the phase sequence is written to a microcode data memory. The drawing data for the graphics mode is sent from the drawing data processor to the microcode processor, and the phase executor instructs the microcode processor to execute the phase sequence to render the desired mode by processing the drawing data. The resulting data is forwarded to another processor for additional microcode processing, vector processing, rasterization, or the like. The ability to select interchangeable phase modules to implement a desired mode reduces microcode memory requirements and allows easy integration and reuse of previously developed features among different games and other graphics software developers without having to rely on the type of platform.

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Copy of Written Opinion for International Application No. PCT/US01/41494, issued on Jun. 26, 2003.
International Search Report for Appln. No. PCT/US01/41494 issued Aug. 1, 2001, 7 pages.

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