Multiplex communications – Channel assignment techniques – Polling
Reexamination Certificate
2004-12-13
2010-06-15
Vu, Thong H (Department: 2465)
Multiplex communications
Channel assignment techniques
Polling
C706S045000
Reexamination Certificate
active
07738484
ABSTRACT:
Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
REFERENCES:
patent: 4646075 (1987-02-01), Andrews et al.
patent: 5315533 (1994-05-01), Stich et al.
patent: 5598348 (1997-01-01), Rusu et al.
patent: 5815299 (1998-09-01), Bayart et al.
patent: 6189106 (2001-02-01), Anderson
patent: 6275905 (2001-08-01), Keller et al.
patent: 6292215 (2001-09-01), Vincent
patent: 6321276 (2001-11-01), Forin
patent: 6330586 (2001-12-01), Yates et al.
patent: 6557069 (2003-04-01), Drehmel et al.
patent: 6650155 (2003-11-01), Nguyen et al.
patent: 6725317 (2004-04-01), Bouchier et al.
patent: 6985502 (2006-01-01), Bunton
patent: 7051218 (2006-05-01), Gulick et al.
patent: 7065688 (2006-06-01), Moyes et al.
patent: 7146510 (2006-12-01), Helms et al.
patent: 7174467 (2007-02-01), Helms et al.
patent: 7509403 (2009-03-01), Lee et al.
patent: 2001/0053694 (2001-12-01), Igarashi et al.
patent: 2002/0059501 (2002-05-01), McKinney et al.
patent: 2002/0138225 (2002-09-01), Wong et al.
patent: 2004/0193706 (2004-09-01), Willoughby et al.
patent: 2004/0236798 (2004-11-01), Srinivasan et al.
patent: 2005/0259696 (2005-11-01), Steinman et al.
patent: 2006/0041696 (2006-02-01), Cherukuri et al.
patent: 2006/0184480 (2006-08-01), Ayyar et al.
patent: 1107266 (1997-08-01), None
patent: 7182225 (1995-07-01), None
patent: WO-03054713 (2003-07-01), None
Office Action for Chinese Patent Application No. 200510107388.6 mailed Nov. 23, 2007, 16 pgs.
Office Action for U.S. Appl. No. 11/011,300, mailed Oct. 7, 2008, 11 pgs.
Office Action for Chinese Patent Application No. 200510119157.7 mailed Dec. 14, 2007, 49 pgs.
Office Action for Chinese Patent Application No. 200510119157.7 mailed May 30, 2008, 11 pgs.
Office Action for Chinese Patent Application No. 200510119157.7 mailed Jul. 13, 2007, 6 pgs.
Final Office Action from U.S. Appl. No. 11/011,300, mailed Jan. 23, 2009, 11 pgs.
Office Action from U.S. Appl. No. 11/011,300, mailed Jun. 18, 2009, 13 pgs.
Office Action for Chinese Patent Application No. 200510107388.6 mailed Jun. 19, 2009, 7 pgs.
First Office Action for Chinese Patent Application No. 200810090191.9 mailed Sep. 18, 2009, 6 pqs.
Ayyar Mani
Chennupaty Srinivas
Jayasimha Doddaballapur N.
Kumar Akhilesh
Mannava Phanindra K.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Vu Thong H
LandOfFree
Method, system, and apparatus for system level initialization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, system, and apparatus for system level initialization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, system, and apparatus for system level initialization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4184767