Method of wet etching low dielectric constant materials

Details Method of wet etching low dielectric constant materials Method of wet etching low dielectric constant materials

2001-08-29

2004-08-24

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C252S079100, C252S079200, C252S079300

Reexamination Certificate

active

06780783

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method of etching low dielectric materials, and more particularly to a method of wet etching low dielectric materials using an aqueous solution.
BACKGROUND OF THE INVENTION
Wafer metallization involves the deposition of thin film of conductive metal onto the wafer using a chemical or physical process. Metal lines conduct the signal through the integrated circuit and dielectric lines insure that signals are not influenced by adjacent lines. The deposition of metal and dielectrics are thin film processes.
With regard to metallization, the term interconnect describes the conductor materials, such as aluminum, polysilicon, or copper, that create the metal wiring that carries electrical signals to different parts of the chip. Interconnect is also used as a general term for the wiring between devices on the die and/the overall package. A contact is an electrical connection at the silicon surface between devices in the silicon wafer and the first metal layer. Vias are openings that extend through the various dielectric layers to form an electrical pathway from one metal layer to the adjacent metal layer. A metal plug fills the vias to form an electrical connection (interconnect) between two metal layers.
An interlayer dielectric is an insulating material that electrically separates and insulates metal levels. After the interlayer dielectric is deposited, the interlayer dielectric is patterned and etched to form via pathways for the various metal layers. This process of creating vias in the interlayer dielectric is repeated for every interlayer dielectric on the die. In traditional processes, a blanket layer of aluminum alloy is deposited on the dielectric layer and then patterned and etched to form metal lines.
FIG. 1
illustrates a semiconductor device having metal interconnect layers and interlayer dielectrics that may be wet etched according to the present invention. A brief description of the structure and the method of manufacturing will provide for a better understanding of the usefulness of the process of the present invention. The semiconductor device is manufactured using a variety of process steps. For example, an epitaxial layer is grown on the wafer. The wafer is cleaned in a number of different chemical baths to remove particles, organic and inorganic contaminants, and native oxide on the wafer. A first level interlayer dielectric is grown on the wafer by flowing oxygen in a process chamber to react with silicon thus producing a silicon dioxide first level interlayer dielectric. A first mask, using a photoresist, is developed and patterned using photolithography with openings therein. The patterned wafer is exposed to high-energy ions that penetrate into the upper surface of the epitaxial layer. For example, phosphorus may be utilized to create the dopant ions creating a n
−
well
14
. Thereafter, the photoresist is stripped, (for example using an ion plasma reactor) and then the wafer is cleaned to remove any residual photoresist. The implanted wafer may be annealed in a furnace to provide a barrier oxide layer and to drive (diffuse) the dopants further into the silicon.
A second photoresist mask is selectively developed over the upper layer of the semiconductor device. Boron ions are implanted into the device through openings in the photoresist to create a p
−
well
16
. Then the product is annealed again.
A barrier oxide layer is formed by placing the wafer in a high temperature oxygen furnace. This protects the active regions in the device from chemical contamination that might occur during subsequent process steps. The wafer is then exposed to a low-pressure chemical vapor deposition furnace in the presence of ammonia and dichlorosilane gases to produce a thin layer of silicon nitride. A third photoresist mask is selectively deposited onto the silicon nitride layer. The photoresist pattern is designed to protect areas of the silicon that are not to be etched. A dry plasma etcher is used to etch trenches in the device.
The etched trench is filled with a silicon dioxide layer
20
by placing the wafer in a high temperature oxide furnace so that silicon dioxide is grown in the exposed walls of the isolation trenches. A nitride mask prevents oxygen diffusion into the active regions. The remainder of the trench is filled with silicon dioxide
22
using low-pressure chemical vapor deposition. The low-pressure chemical vapor deposition of silicon dioxide also covers the entire wafer surface. Therefore, an oxide chemical mechanical planarization step is conducted.
A thin layer of silicon dioxide
24
may be grown on the wafer. Thereafter, polysilicon is deposited using low-pressure chemical vapor deposition with silane. A fourth mask is patterned and developed. A plasma is utilized to remove unwanted polysilicon and to leave a polysilicon gate
26
.
A fifth mask is patterned and developed, and a lightly doped n
−
well is formed in the device using for example arsenic or phosphorus. Thereafter the fifth mask is removed. A sixth mask is selectively deposited over the device and lightly doped n
−
drain
30
areas are implanted using boron or boron difluoride.
Side wall spacers
32
may be formed by depositing silicon dioxide using chemical vapor deposition. This layer of silicon dioxide is used to form spacers on the sides of the polysilicon gates. A plasma etcher is used to remove most of the oxide leaving behind sidewalls on the polysilicon gate.
A seventh mask is selectively developed on the device and a high dose of arsenic is implanted to form n
+
source/drain regions
34
are formed and the photoresist removed. Similarly, an eighth mask is selectively deposited and a high dose of boron is implanted to form p
+
source/drain regions
36
are implanted into the device and the photoresist removed.
Metal contacts
38
are formed over the active regions of the silicon. Preferably, titanium is deposited on the wafer using a sputtering process. The wafer is annealed in a furnace to trigger a chemical reaction between the titanium and the silicon to form tisilicide. The unwanted titanium is etched away leaving behind a metal contacts over the active regions of the silicon.
A barrier layer of silicon nitride (not numbered) is preferably deposited using a chemical vapor deposition process. The silicon nitride protects the active regions. Thereafter a local interconnect oxide layer
40
is deposited over the silicon nitride layer. Preferably the local interconnect oxide layer is doped silicon dioxide. Chemical mechanical planarization is performed on the local interconnect oxide layer. Thereafter, a ninth mask is selectively deposited on the wafer and trenches are etched through the first level interlayer dielectric.
A thin layer of materials such as titanium (not numbered) is deposited into the trenches formed in the first level interlayer dielectric. The titanium nitride layer (not numbered) is deposited over the titanium to serve as a diffusion barrier. The trench is filled with tungsten using a chemical vapor deposition step that coats the entire wafer. A chemical mechanical planarization step is performed to polish the tungsten down to the local oxide thus forming a first portion of a metal plug (interconnect)
42
in the local oxide portion of the first level interlayer dielectric.
A first level interlayer dielectric
44
is deposited over the local interconnect oxide using chemical vapor deposition. Oxide chemical mechanical planarization is used to planarize the first level interlayer dielectric
44
. Thereafter, a 10th mask is selectively developed on the first level interlayer dielectric
44
and vias are etched through the dielectric down to the tungsten. A thin layer of titanium is deposited across the surface of the wafer using physical vapor deposition. The titanium will line the walls of the via holes formed in the first level interlayer dielectric. Titanium nitride is thinly deposited on top of the titanium layer to serve as a diffusion barrier for the tungsten that will be de

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