Method of verifying circuit and computer-readable storage...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing

Reexamination Certificate

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C716S107000, C716S111000

Reexamination Certificate

active

07996802

ABSTRACT:
A method of verifying a circuit for use in an apparatus for verifying a circuit operation indicated by circuit information, the circuit including a plurality of logic circuits and at least one connection line between the logic circuits, the method includes: obtaining information of a plurality of pieces of asynchronous circuits from the circuit information; determining information of asynchronous circuits of a first type and a second type stored in a library; extracting information of an asynchronous circuit of a third type including the asynchronous circuits of the first type and the second type; and extracting verification information associated with the information of the asynchronous circuit of the third type, for verifying the circuit.

REFERENCES:
patent: 5469367 (1995-11-01), Puri et al.
patent: 6088821 (2000-07-01), Moriguchi et al.
patent: 6170072 (2001-01-01), Moriguchi et al.
patent: 6557161 (2003-04-01), Jones
patent: 2002/0188912 (2002-12-01), Kondratyev
patent: 2006/0190851 (2006-08-01), Karaki et al.
patent: 2007/0040586 (2007-02-01), Sakamaki et al.
patent: 2009/0106719 (2009-04-01), Stevens
patent: 2010/0316142 (2010-12-01), Tsuchiya et al.
patent: 2000-11031 (2000-01-01), None
Morin-Allory, K, et al. “Asynchronous Assertion Monitors for Multi-Clock Domain System Verification”, Seventeenth IEEE International Workshop on Rapid System Prototyping, Jun. 2006, pp. 223-228.
Chong, K et al. “A Simple Methodology of Designing Asynchronous Circuits using Commercial Design Tools and Standard Library Cells”, ISIC 2007, International Symposium on Digital Object Identifier, Sep. 2007, pp. 176-179.
Nelson, C.A., et al. “Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits, Mar. 2007, pp. 592-605.
Yavuz-kahveci, T., et al. “Verificationof Parameterized Hierarchical State Machines using Action Language Verifier”, Proceedings , Third ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005, pp. 79-88.

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