Method of verifying a layout pattern

Details Method of verifying a layout pattern Method of verifying a layout pattern

2011-03-22

2011-03-22

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Analysis and verification

C716S050000, C716S051000, C716S052000, C716S054000, C716S056000, C430S005000, C430S030000

Reexamination Certificate

active

07913196

ABSTRACT:
A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.

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“Layout Manufacturability Analysis Using Rigorous 3-D Topography Simulation”, by Andrzej J. Strojwas, Zhengrong Zhu, Dennis Ciplick and Xiaolei Li, IEEE @2001.

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