Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
1999-11-01
2002-12-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C257S691000, C257S700000, C257S707000
Reexamination Certificate
active
06495399
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of electronic packaging technology, and specifically to a vacuum type of electronic packaging technology used with air gap interconnect semiconductor chips.
BACKGROUND OF THE INVENTION
Modern integrated circuit semiconductor devices are complex three-dimensional structures with metallized conductor lines, such as interconnects, separated or insulated by interlayer dielectrics. Inorganic materials, such as silicon dioxides (SiO
2
) and silicon nitride (Si
3
N
4
), are conventionally used as these interlayer dielectrics.
Recently, the photo-definable derivatives of certain polymeric materials, such as polyimides, silicone-polyimides, and benzocyclobutenes, have become widely used as interlayer dielectrics because they tend to have lower dielectric constants (k) compared to inorganic interlayer dielectrics. A lower-k interlayer dielectric reduces the signal propagation delays and enhances the system performance. For example silicon dioxide has a dielectric constant of about 4, while Teflon® is a material that has one of the lower dielectric constants, i.e. about 2.0 (Air has a dielectric constant of
1
). However Teflon® has certain characteristics and process issues that must be addressed before it can be widely used.
The major functions of electronic packaging are to: a) support and protect the chip from hostile environments; b) distribute the signals onto and off of the silicon chip; c) provide a path for the electrical current that powers the circuits on the chip; and d) remove the heat generated by the circuits.
Back end-of-line (BEOL) resistance capacitance (RC) is becoming increasingly important in ultra large-scale integration (ULSI) where an integrated circuit (IC) contains over 10 million semiconductor devices, and thus where the design rule approaches 0.25 &mgr;m and smaller.
U.S. Pat. No. 5,866,442 to Brand et al. describes a semiconductor device assembly with a semiconductor device spaced apart from a substrate to define a gap to be filled by a fill material. The substrate has thermal vias formed therein and after the semiconductor device is connected to the substrate and the fill material is positioned about the gap to form a seal, a vacuum is drawn through the thermal vias and a pressure is applied to the fill material to urge the fill material into the interior of the gap.
U.S. Pat. No. 5,766,987 to Mitchell et al. describes methods and equipment whereby microelectronic assemblies such as semiconductor chip assemblies are encapsulated. Covering layers not only protect both the terminals carried by a dielectric layer and the bottom surface of the semiconductor chips in each assembly, but also confine a liquid encapsulant and prevents contamination of the terminals and the chip bottom surfaces. The liquid encapsulant and the assemblies are placed into a tilting fixture, the fixture is closed and evacuated, and the encapsulant is then poured onto the assemblies while maintaining the fixture under vacuum. The fixture is then pressurized during cure of the encapsulant.
U.S. Pat. No. 5,401,687 to Cole et al. describes a method for preserving an air bridge structure on an integrated circuit chip used in an overlay process. A patternable protective layer is applied for mechanical strength to prevent deformation during subsequent processing. A polymeric film layer is applied over the chip and protective layer and interconnections are fabricated through the polymeric film layer. The polymeric film layer is removed from the area over the air bridge structure and the protective layer is then removed leaving the resultant structure with an undamaged air bridge free of residue.
U.S. Pat. No. 5,798,557 to Salatino et al. and U.S. Pat. No. 5,915,168 to Salatino et al. (a divisional of the Salatino U.S. Pat. No. 5,798,557 Patent), describe a packaged integrated circuit (IC) and method of making same, respectively, where the IC is a wafer level hermetically packaged IC that has a protective cover wafer bonded to a semiconductor device substrate wafer. The substrate wafer may contain a cavity. The cover wafer seals integrated circuits and other devices such as air bridge structures, resonant beams, surface acoustic wave (SAW) devices, trimmable resistors and micromachines. Some devices are formed on the surface of cavities formed in the protective cover wafer. Dies are separated to complete the process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor chip device package having a vacuum within interconnect voids in the semiconductor chip device to reduce the interconnective RC delay and prevent metal corrosion.
Another object of the present invention is to provide a low cost packaging technology which changes the dielectric k-value to reduce the interconnective RC delay and prevent metal corrosion.
Yet another object of the present invention is to provide a method of forming a packaged semiconductor assembly by drawing a vacuum on an entire air gap semiconductor device to form a vacuum within the voids separating the interconnects.
A further object of the present invention is to provide a semiconductor chip device package having a vacuum within interconnect voids in the semiconductor chip device to lower the interlevel dielectric constant to reduce the signal propagation delays and enhance the system performance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor chip device package is comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.
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Ang Ting Cheong
Loong Sang Yee
Ong Duay Ing
Quek Shyue-Fong
Chartered Semiconductor Manufacturing Ltd.
Chaudhuri Olik
Ha Nathan W.
Pike Rosemary L. S.
Saile George O.
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