Method of using logical names in post-synthesis electronic desig

Details Method of using logical names in post-synthesis electronic desig Method of using logical names in post-synthesis electronic desig

1995-08-31

1998-03-10

Teska, Kevin J.

Boots, shoes, and leggings

364578, G06F 1716

Patent

active

057271879

ABSTRACT:
A method used by an electronic design automation system for allowing the use of logical names from a register transfer level description of an integrated circuit design in timing notes and simulation tests written for timing analysis and simulation programs. A synthesis program generates a state map file containing an entry for the logical name for each state defined in the register transfer level description of the integrated circuit. The gate level name generated by the synthesis program corresponding to the logical state name is stored in the entry providing a one to one mapping of a logical state name to a gate level state name. The state map file is input to timing analysis and simulation programs wherein references to the logical state names in timing notes and simulation tests are translated to gate level state names before further processing.

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