Method of using disposable hard mask for gate critical dimension

Details Method of using disposable hard mask for gate critical dimension Method of using disposable hard mask for gate critical dimension

1995-05-05

1996-08-13

Fourson, George

Fishing, trapping, and vermin destroying

437193, 437195, 437228, H01L 2128

Patent

active

055455883

ABSTRACT:
A new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light. The semiconductor layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer. The semiconductor layer, the spin-on-glass layer, and the polysilicon layer not covered by the photoresist mask are anisotropically etched away to form polysilicon gate electrodes and interconnection lines. The photoresist mask, the hard mask, and the spin-on-glass layer are removed to complete the formation of polysilicon gate electrodes and interconnection lines having uniform critical dimension in the fabrication of an integrated circuit.

REFERENCES:
patent: 5219788 (1993-06-01), Abernathy et al.
patent: 5302538 (1994-04-01), Ishikawa et al.
patent: 5324689 (1994-06-01), Yoo
patent: 5350486 (1994-09-01), Huang
patent: 5354713 (1994-10-01), Kim et al.

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