Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
1999-03-08
2001-05-29
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S695000, C438S696000, C438S699000, C438S703000, C438S712000, C438S725000, C438S749000
Reexamination Certificate
active
06238936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to techniques which are used during the fabrication of semiconductor devices. More specifically, the invention relates to a technique which uses multiple mappings of critical dimensions of selected features formed on a wafer during the process of forming integrated circuits, to enable a new etch process to be qualified in an efficient manner and with particular regard to mitigating effects which are encountered during the various steps which are carried during the constructive processes.
2. Description of the Related Art
When a new etch process is introduced, it is difficult to predict the exact results which will be achieved using the same. Accordingly, it is necessary to conduct tests which will reveal the degree to which a positive or negative bias, or other effects such as incomplete etching, overetching including undercutting and/or resist lifting etc., have on the type of etching process being used.
In the case of wet etching of silicon, it is common to use a solution of nitric and hydrofluoric acids. Depending on the ratio of the acids (viz., the recipe) the reaction can be rendered exothermic wherein the heat which is generated tends to speed up the etching process. In order to attenuate the run-away reaction being initiated it is necessary to exert some degree of control and add some modulating agent such as acetic acid or the like. A further factor influencing the process is the crystal orientation which can be used to control the shape of the bottom of a trench which is being created.
Hydrofluoric acid is widely used to etch silicon dioxide. However, in this instance also the recipe is of importance. For example, hydrofluoric acid is usually mixed with water and is buffered with ammonium fluoride to attenuate the generation of hydrogen ions which tend to accelerate the rate of etching. In the case of aluminum problems can be experienced in the event that tiny bubbles of hydrogen gas are produced. These bubbles tend to adhere to the surfaces which are being etched and caused localized slowing of the process. The lack of uniformity of material removal and/or and unexpectedly low etching degree is thus experienced.
In the case that etching of silicon nitride is required, a problem is encountered in that it is necessary to use hot phosphoric acid and, apart from the problems that handling this type of material at temperatures of about 180° C. also tends to cause thermal damage to the resist which is being used as the etch mask.
An example of wet etching which uses a combination of potassium hydroxide, ethylene glycol and water is disclosed in U.S. Pat. No. 3,909,325 issued on Sep. 30, 1975 to Church et al. This reference is hereby incorporated herein by reference.
Dry etching on the other hand. can include plasma, ion milling and reactive ion etching (RIE). As is well known, in the case of plasma etching, gases are introduced at controlled rates while the pressure in the chamber is reduced. The plasma is activated through the application of power at a selected radio frequency or frequencies. However, the effect of temperature, especially the surface temperature of the substrate being etched, must be carefully monitored along with other factors such as the flow rate of the reactants, the ion density, chamber pressure, etc. Further, the effects of plasma/radiation damage must be taken into consideration.
An example of plasma etching is given in U.S. Pat. No. 4,115,184 which was issued on Sep. 19, 1978 in the name of Poulsen. The content of this document is hereby incorporated herein by reference.
However, in the event that a new etch process is being introduced to a production line, it is necessary to taken a large number of factors into consideration depending on the type of etching and the substrate involved. Therefore, the random type of approach of determining which factors require adjustment and the direction of adjustment that is necessary tends to require an excessive amount of experimentation.
Accordingly, there exists a need for a reliable technique by which a new etch process can be introduced and qualified in a manner which identifies the problems that need to be addressed in order to achieve production set-up quickly and relatively inexpensively.
SUMMARY OF THE INVENTION
The present invention provides a technique wherein a type of feedback control can implemented in a manner that enables the calibration or qualification of a new etch process. The underlying inventive technique is based on a sequence of mappings which are carried out at each of a number of production stages, and wherein critical dimension (CD) data, accumulated during each of the mappings, are examined, compared and used to determine what adjustments can be made to ensure that the closest possible adherence to the design requirements is achieved.
The present invention, therefore, enables generation of a feedback control data base. For example, if the mapping of results of the etching are examined and it is found that a line width or corner is too great or too small, or the configurations of given features are not as good as is required to assure the best performance of the device (e.g., features necessary to optimize the speed performance of a microprocessor for example) then it is possible to determine through analysis of the data, what adjustments/changes need to be made to the etch process or processes to ensure that improvements are made and a better product is realized.
In brief, in order to improve the quality of a semiconductor product, mapping of the critical dimension of predetermined features such as ring oscillators, test transistors, turning forks wafer electrical testing-purpose (WET) transistors etc., is carried out at various stages of the process. For example, a reticle is mapped, the etch mask which is produced from the effect of the image on the resist layer, and the results of the etching is respectively mapped. Using the data gleaned from these mappings it is possible to determine from the end result, if any of the control variables of a new etch process require adjustment to improve the quality of the end product. Thus, when a etch process is introduced to the process, it is possible to run the process and then work back via the collected critical dimension data to determined what changes in the control parameters are appropriate in order to improve the fabrication result.
More specifically, a first aspect of the present invention resides in a method of qualifying an etch process which is used in connection with the fabrication of integrated circuits, the method comprising the steps of: mapping the critical dimensions of a predetermined plurality of features at each of a plurality of selected exposure fields of at a predetermined number of production stages including an etch step, of a wafer on which a plurality of integrated circuits are fabricated; comparing sets of data collected at each of the mappings; and determining, based on the comparison, what changes are required in control parameters of the etch step, to bring at least one critical dimension of at least one of the predetermined features into agreement with at least one of a predetermined set of design critical dimensions. In this method the predetermined features comprise ring oscillators, turning forks, test transistors, and wafer electrical testing-purpose (WET) transistors.
A second aspect of the present invention resides in a method of qualifying an etch process used in the production of integrated circuits, the method comprising the steps of: sequentially exposing a predetermined number of exposure fields on the wafer using a photolithic or electron beam exposure technique; developing an etch mask; mapping the etch mask to determine a first set of critical dimension data for all features that impact integrated circuit speed performance, including ring oscillators, turning forks, test transistors, and WET transistors, which are located in the exposure field, which are contained in a selected group of the predetermi
Advanced Micro Devices , Inc.
Elms Richard
Luu Pho
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