Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-03-08
2002-02-05
Grant, William (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C250S492220, C430S005000
Reexamination Certificate
active
06345211
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to techniques which are used during the fabrication of semiconductor devices. More specifically, the invention relates to a technique which uses multiple mappings of critical dimensions of selected features formed on a wafer during the process of forming integrated circuits, to enable a new fabrication/manufacturing process to be calibrated/qualified in an efficient manner and to enable the production of an a microprocessor chip wherein the speed of the processor is optimized.
2. Description of the Related Art
The speed of a processor is dependent on the degree of accuracy with which the individual features of its integrated circuit (IC) are manufactured. For example, if a line has a curve or bend in it and the width of the line varies, e.g. narrows, then the amount of resistance of the line will vary and the resulting speed with which data is transferred from one point to another will be affected/impaired. In addition, heat will be generated at the narrower, higher resistance locations. With the development of localized heating, the amount of resistance tends to be increased. This process can, of course, in the worse case scenario, escalate until such time as a hot spot causes the line to fail and the circuit associated therewith is highly impaired or rendered inoperative.
Accordingly, the process of manufacturing the microprocessor needs to be examined in order to ensure that all of the features which impact the speed and efficiency are being formed optimally and free of defects of the nature alluded to above.
The term process or method should be understood throughout the following disclosure to mean at least the combination of a number of different process or method steps including resist coating, exposure via a reticle/photolithographic operation or election beam scanning, etch/implantation mask formation, etching or implantation, etc. This term should also be taken to include the use of hardware which affect the processes or methods being carried out. For example, in order to assure the correct processing is carried out, it is necessary to ensure that the operation of a stepper and associated robotics and transport mechanisms, for example, are appropriately calibrated, the etch mixtures/recipes are tuned to the required levels to avoid under or over etching, undercutting and the like.
Calibration or qualifying of the stepper is necessary before production can begin. It is also necessary to calibrate the operation of the wafer track and associated robotics in order to determine that the wafer is being moved between and disposed in the stepper and processing chambers (e.g. etching chambers) in an optimally correct manner, and thus assure that the wafer is reproducibly set on the table of the stepper in a correctly oriented and located position, each and every time.
Further, during the fabrication of an integrated circuit (IC) it is necessary to impress images on resist coating and to etch, deposit, implant or the like, a number of times before the devices on the wafer are completed and the wafer is ready for dicing. It is, therefore, necessary to ensure that the hardware used to move the wafer(s) back and forth, manipulate and to photolithograph, is operating in a manner such that each and every wafer undergoes the same manipulations/operations during each and every stage of production. For example, accurate reproducible location of the wafer in the stepper is necessary. U.S. Pat. No. 5,392,361 issued on Feb. 21, 1998 in the name of Imaizumi et al., discloses the use of a mark on the wafer and a mark position detecting method and apparatus which uses fuzzy logic to improve alignment accuracy.
For further examples of the type of arrangements which are associated with the tool set, reference can be had to U.S. Pat. No. 4,641,071 issued in Feb. 1987 in the name of Tazawa et al, and U.S. Pat. No. 4,719357 issued in Jan. 1998 in the name of Ayata et al.
It is also necessary to ensure that all of the other processes which are conducted during the IC fabrication are also working in “concert” with the hardware and the computer
umerical controls which are associated therewith. Feedback arrangements which monitor the temperature of the surface of tile wafer during plasma etching, for example, should it be used during the fabrication, is preferably checked to see if the parameter is being accurately detected and reported.
With respect to the etching process which inevitably form part of the manufacturing process, reference may be had to U.S. Pat. No. 3,909,325 issued on Sep. 30, 1975 to Church et al. which discloses an example of wet etching that uses a combination of potassium hydroxide, ethylene glycol and water. This reference is hereby incorporated herein by reference. For an example of plasma etching, reference may be had to U.S Pat. No. 4,115,184 which was issued on Sep, 19 1978 in the name of Poulsen. The content of this document is also incorporated herein by reference.
However, no matter what measures are taken, in the final analysis, the only way of determining if all of the necessary adjustments have in fact been made in all optimal manner is to make a test run and to examine the end product (viz., conduct empirical testing). However, this technique tends to leave it to chance as to which adjustment or setting needs to be fine tuned to bring this highly complex arrangement into truly optimal operational status. That is to say, the settling and arrangeent of the reticle which is set in the optics of the stepper must be carefully examined in order to determine if adjustments to this vital piece of apparatus is necessary to correct some less than desirable outcome of the IC production.
Accordingly, the present invention provides a type of feedback of approach. For example, an adjustment to the stepper operation, the robotics which move the wafers from the wafer track to the stepper table, the position to which the wafer track moves the wafers prior transfer, in combination with a possible change in the reticle or even an resist or etching recipe, may, even though it would appear contrary to what might be conventionally considered to be correct and/or appropriate, enable the end result to be improved.
Nevertheless, without some form of sophisticated analysis which can be carried out in a reliable and reproducible manner, the above types of adjustment and changes in technique amount to nothing more than guess work. Accordingly, there remains a need for a reliable technique via which microprocessor speed performance can be optimized through the identification of the problem which need to be addressed in order to achieve the required speed performance optimization.
SUMMARY OF THE INVENTION
The present invention provides a technique wherein a type of feedback control, based on accumulated critical dimension (CD) mapping data of a suitably large number of different features which are produced in an integrated circuit (IC) arrangement, is implemented in a manner that enables the optimization of microprocessor speed performance.
More specifically, the underlying technique is based on a sequence of mappings which are carried out at each of a select number of production stages/steps, and wherein CD data is accumulated during each of the mappings is examined, compared and used to determine what adjustments should be made at various stages of the manufacture to ensure that the closest possible adherence to the design requirements and, therefore, the speed performance of the microprocessor, is achieved.
In other words, the present invention enables the use of an effective to feedback control data base. For example, if the mapping of results of the etching are examined and it is found that a line width or corner is too great or too small, or the configurations of given features are not as good as is required to assure the best performance of the device (e.g., features necessary to optimize the speed performance of a microprocessor), then it is possible to determine what adjustments can/should be
Advanced Micro Devices , Inc.
Grant William
Hartman Jr. Ronald D
LandOfFree
Method of using critical dimension mapping to optimize speed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of using critical dimension mapping to optimize speed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of using critical dimension mapping to optimize speed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2943223