Method of using complementary logic gates to test for faults in

Details Method of using complementary logic gates to test for faults in Method of using complementary logic gates to test for faults in

1985-01-28

1987-06-16

Fleming, Michael R.

Excavating

324 73R, G06F 1100, G01R 3128

Patent

active

046740902

ABSTRACT:
A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.

REFERENCES:
patent: 4061908 (1977-12-01), de Jong
patent: 4363124 (1982-12-01), Aichelmann
patent: 4369511 (1983-01-01), Kimura
patent: 4503387 (1985-03-01), Rutledge
patent: 4503536 (1985-03-01), Panzer
Foster et al, "Checking Associative Store Address Line Drivers," IBM Tech. Disc. Bull., May 1971, pp. 3867-3868.

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