Boots – shoes – and leggings
Patent
1996-06-27
1998-10-06
Teska, Kevin J.
Boots, shoes, and leggings
364490, G06F 9455
Patent
active
058190724
ABSTRACT:
Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.
REFERENCES:
patent: 4695968 (1987-09-01), Sullivan, II et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5051938 (1991-09-01), Hyduke
patent: 5062067 (1991-10-01), Schaefer et al.
patent: 5095454 (1992-03-01), Huang
patent: 5191541 (1993-03-01), Landman et al.
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5384720 (1995-01-01), Ku
patent: 5400270 (1995-03-01), Fukui
patent: 5404311 (1995-04-01), Isoda
patent: 5448497 (1995-09-01), Ashar et al.
patent: 5457638 (1995-10-01), Ashar et al.
patent: 5508937 (1996-04-01), Abato et al.
patent: 5572717 (1996-11-01), Pedersen
patent: 5596505 (1997-01-01), Steinweg et al.
patent: 5623418 (1997-04-01), Rostoker et al.
patent: 5657239 (1997-08-01), Grodstein et al.
Bushard Louis B.
Criswell Peter B.
Fuller Douglas A.
Paul Richard F.
Rezek James E.
Fiul Dan
Johnson Charles A.
Starr Mark T.
Teska Kevin J.
Unisys Corporation
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