Method of trench polishing

Details Method of trench polishing Method of trench polishing

1998-10-01

2001-09-18

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Radiation modifying product or process of making

Radiation mask

C430S296000, C430S314000, C430S317000, C430S322000, C438S437000

Reexamination Certificate

active

06291111

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113159, filed Aug. 11, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of trench polishing, and more particularly, to a method of fabricating a shallow trench isolation (STI) by using a reverse active mask.
2. Description of the Related Art
The fabrication line width of semiconductor fabrication process is developed towards a wavelength shorter than 1 &mgr;m as the design of integrated circuit becomes more and more complex. The very short line width limits the development of forming trench isolation in complementary metal-oxide semiconductor (CMOS). In the conventional technique of a planarization process by chemical mechanical polishing (CMP), if the underlying layer having a pattern with a pitch larger than 10 &mgr;m, a dish-like recess is formed in the active region after planarization. The requirement of a global planarization thus can not be achieved. This is the so-called “dishing effect”.
FIG. 1A
to
FIG. 1D
are cross sectional views showing a method of fabricating a shallow trench isolation by chemical mechanical polishing.
In
FIG. 1A
, a pad oxide layer
11
is formed on a substrate
10
. A dielectric layer
12
is formed on the pad oxide layer
11
. Using photolithography and etching process, the dielectric layer
12
is patterned to define a device region
13
covered by the patterned dielectric layer
12
. The substrate
10
is then etched to form trenches as shown in the figure. In
FIG. 1B
, a silicon oxide layer
14
is formed over the substrate
10
to fill the trenches by chemical vapor deposition (CVD). By chemical mechanical polishing, the silicon oxide layer
14
is planarized with the dielectric layer
12
as a polishing stop, so that oxide plugs
15
and
16
are formed as shown in FIG.
1
C. The dielectric layer on the active region
13
is then removed to form the shallow trench isolation structure.
It is known that the area of each isolation structure is not identical. As shown in
FIG. 1C
, the area of the shallow trench isolation
16
is much bigger than the area of the shallow trench isolation
15
. The shallow trench isolation
16
with a larger area has a recessed surface after being polished. In
FIG. 1D
, while planarizing a polysilicon layer
18
formed on the substrate
10
subsequently, a global planarization thus cannot be achieved.
In the conventional method of fabricating a shallow trench isolation, a reverse diffusion layer mask and an etch back process for an oxide layer are used to achieve the uniformity of chemical mechanical polishing. However, as the line width is reached 0.25 &mgr;m or even lower, the design rule is so tight that it is easy to cause misalignment during exposure. The problem of overlapping pattern occurs.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a chemical mechanical polishing process of fabricating a shallow trench isolation. A reverse active mask is used to solve the problem of overlapping patterns caused by misalignment or error during exposure.
To achieve the above-mentioned objects and advantages, a method of trench polishing. A semiconductor substrate is provided. A photo-mask with a pattern is provided. The method of fabricating the photo-mask further comprising providing an original pattern which comprises a plurality of active regions with individual size. The original pattern is enlarged outwards to connect and merge some of the active regions. The active regions is diminished inwards until some small active regions eliminate, the diminished line width being denoted as B. A reverse treatment is performed to obtain a reverse pattern. The reverse pattern is enlarged with a line width C. The reverse pattern is combined with the original pattern. The substrate is patterned with the photo-mask with the combined pattern. An insulation layer is formed on the substrate. The insulation layer is polished.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5208124 (1993-05-01), Sporon-Fiedler
patent: 5902752 (1999-05-01), Sun
patent: 5926723 (1999-07-01), Wang
patent: 5926733 (1999-07-01), Heo
patent: 5998280 (1999-12-01), Bergemont

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