Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2005-04-22
2008-12-09
Ward, Jessica (Department: 1793)
Metal fusion bonding
Process
Plural joints
C228S103000, C228S104000
Reexamination Certificate
active
07461771
ABSTRACT:
A method of treating a via connected with a substrate and a method of probing the via are disclosed. A pattern of a lead-free solder paste is applied around a hole of the via without completely covering a pad of the via. The paste is reflowed to form a pattern of a lead-free solder on a pad that covers only a portion of a surface area of the pad and is positioned around the hole. The solder may be substantially symmetrically positioned around the hole. A flux generated during reflow is insufficient to plug the hole. The lead-free solder can be probed by a blade probe including colinear first and second edges and having a preferred orientation relative to the pattern of the lead-free solder.
REFERENCES:
patent: 5875102 (1999-02-01), Barrow
patent: 6395995 (2002-05-01), Joy et al.
patent: 6809535 (2004-10-01), Campbell
patent: 6833615 (2004-12-01), Geng et al.
patent: 7025628 (2006-04-01), LaMeres et al.
patent: 2003/0234441 (2003-12-01), Delheimer
patent: 2004/0099716 (2004-05-01), Yuan et al.
patent: 2007/0018663 (2007-01-01), Leinbach et al.
Joh O'Connell, Study and recommendatins into using lead free printed circuit board finishes at manufacturing in circuit test stage, Agilent Technologies Electronic Manufacturi, Aug. 8, 2004.
David Suraski Aim & Matt Parker, Considerations for the pin probe testing of no-clean solder paste residues, date unavailable.
John M Radman, Guide to testing lead-free product, Trace laboratories-east Technical Spotlight, date unavailable.
Challenges and opportunities in lead-free solder PCB assembly, Global SMT & Packaging ,Oct. 2002 , www.globalsmt.net.
Dr Dongkai Shangguan, Study of Compatibility for lead-free solder PCB Assembly, Flextronics San Jose, CA, date unavailable.
Kevin Hu, Recommended Design, Integration and Rework Guidelines for International Rectifier's BGA and LGA Packages, International rECTIFIER Applicatin Note an-1028.
Lee W Ritchey, Anatomy of a Plated Through Hole, Copyright, speeding edge Oct. 2, 2001.
Lead Poisoning affects thousands of children and adults, www.lead-poisoning-news.com.
Jill Schildhouse, EU leading the lead-free way, Feb. 2005 Inside supply anagement, vol. 16, No. 2, p. 20.
Rob Spiegel, Threat of tin whiskers haunts rush to lead-free, Electronic new, Mar. 17, 2005.
Matt Parker & Jeff Smith, PCB testing goes socketless, Fixture Probing.
Basic Terminology, Technical Source Book, Interconnect Devices, inc.
Technical Summary Definitions, Technical Source Book, www.idinet.com.
Applications note OSPS and Rotators, Entek Plus, Interconnect Devices, Inc.. www.idinet.com, date unavailable.
Applications note Approaches to Sharp Chisels for Contaminated PCB Test, The need for sharp chisels; www.idinet.com, date unavailable.
OSP Coated Pads—Point Style Selection, www.qatech.com/tech/appliation—note/AN18.htm.
Recommended Point Styles, www.qatech.com/tech/applications—notes/AN09.htm.
How Probe Tip Geometry Affects Contact Reliablity, www.qatech.com/tech/appliations—notes/an02.htm.
IDI—Technical Source Book—OSP's and Rotators, www.idinet.com/tech/sourcebook/index.asp?ids=002CB4-FC1b2A0&Page=19.
Assessing Life-Cycle Impacts in the Electronics Industry; Design for the Environment, Lead Free solder Partnership.
Common failure Modes for test Probes, www.qatech.com/tech/applications—notes/AN04.htm.
Aboagye Michael
Hewlett--Packard Development Company, L.P.
Ward Jessica
LandOfFree
Method of treating and probing a via does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of treating and probing a via, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of treating and probing a via will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4030736