Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2000-10-02
2004-11-09
Ingberg, Todd (Department: 2124)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C712S200000, C712S204000, C712S210000, C712S221000
Reexamination Certificate
active
06817012
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of translating a source operation to a target operation. For example, the method may be used to permit efficient computation with integer values whose bit-width is not a multiple of a native integer bit-width of a target machine, such as a computer. Another application of such a method to in the simulation of high-level hardware description languages. The invention also relates to a computer program for performing such a method, a storage medium containing such a program, a computer programmed by such a program and a translation produced by such a method.
2. Description of the Related Art
Hardware description languages such as VHDL (IEEE Computer Society.
IEEE Standard VHDL Lanquage Refrence Manual
. New York, USA. June 1994. IEEE Std 1076 1993 and Verilog HDL (IEEE Computer Society.
IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language
. New York, USA. 1996. IEEE Std 1364 1995.) can be used to describe the behaviour of hardware circuits. These languages support the description of circuits involving integer arithmetic by supplying appropriate numeric types and operators. In order to design hardware efficiently, the numeric types are usually parameterised by the bit-widths of the integer values of the type.
For instance, the IEEE 1076.3 NUMERIC_STD VHDL library (IEEE Computer Society. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description language, New York, USA, 1996. IEEE Std 1364 1995) defines the UNSIGNED and SIGNED integer types based on the type of bit vectors STD_LOGIC VECTOR. Bit vectors are fixed-length lists of bit values which include the values 0 and 1 as well as other states such as U (uninitialised) and Z (high impedance). Although the length of the bit vectors (and therefore of the numeric types) is fixed, one can use several types of bit vectors (each having different lengths) in a hardware design. Note that since the individual bits of a VHDL numeric type can have values other than 0 and 1, a numeric type contains several values that do not correspond to valid integers.
High-level hardware description languages, such as the Bach language (Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, Andrew Kay, Toshio Nomura and Takashi Kambe. Hardware synthesis with the BACH system. International Symposium on Circuits and Systems, 1999, GB2 317 245), can be used to describe hardware at a level of abstraction usually used in programming languages such as C (Brian W. Kernihan and Dennis M. Ritchie. The C Programming Language, Prentice-Hall, USA, second edition, 1988).
Since the C language, and programming languages in general, are designed to be used to program some particular architecture, the semantics of their integer types and expressions usually depend on the target architecture being programmed. For example, the C language (Brian W. Kernihan and Dennis M. Ritchie. The C Programming Language, Prentice-Hall, USA, second edition, 1988) supplies the int and unsigned int types which correspond to signed and unsigned integers whose bit-width is naturally supported by the target machine. The C integer types are too inflexible to be used for the efficient design of hardware and therefore the Bach hardware description language extends C by exact width integer types, such as intw and unsigned into for signed and unsigned v-bit integers, respectively.
One of the many advantages of using a high-level, programming-language based, hardware description language like Bach over using a lower level one such as VHDL is the ability to simulate (on a general purpose architecture) the behaviour of designs at much higher speeds. For example, because of the particular level of abstraction of the VHDL numeric types described earlier, one cannot use the integer arithmetic of the target machine used for simulation directly. In general, one would have to represent every bit value of a numeric type as a separate byte/word on the target machine and therefore the simulation of VHDL arithmetic operations can be much slower than the native arithmetic of the target machine. Although Bach arithmetic is more similar to the native arithmetic of a target machine than VHDL numeric arithmetic is, one still cannot use the native target machine arithmetic naively because of the difference in the bit-widths. One therefore needs to develop methods for the correct and efficient simulation of the exact width of the arithmetic usually used in hardware descriptions.
Retargetable compilers, such as the Valen-C compiler (Graduate School of Information Science and Electrical Engineering (Kyushu University), Advanced Software Technology and Mechatronics Research Institute of Kyoto, Institute of Systems and Information Technologies (Kyushu) and Mitsubishi Electric Corporation.
Valen
-
C Compiler Development Ddocument
(
English Version
1.01). Information Technology promotion Agency, Japan, April 1998), can be used to compile an input source program to the assembly/machine language of different target machines. The input language of the Valen-C compiler is the Valen-C programming language which also extends the ANSI C language by exact width integer types. The programmer can specify integer types of the form intw where w is any non-zero natural number representing the width of the type. However, the semantics of the Valen-C integer arithmetic is still dependent on the target architecture and an integer type intw is actually defined as being at least w bits long and Its width is a multiple of the word size of the target machine. As a result, the behaviour of the compiled code differs from one target machine to another.
De Coster et al, “Code generation for compiled bit-time simulation of DSP applications”, 11
th
International Symposium on System Synthesis (ISSS'98) 2-4 Dec. 1998, Hsinch, Taiwan (IEEE Computer Society Publications) pp 9-14 disclose a method intended for translating, fixed point integer arithmetic into standard integer arithmetic for the efficient simulation of digital signal processing (DSP) applications. However, no attempt is made to minimise value correcting operations in the resulting integer arithmetic expressions, which thus make inefficient use of target machine resources.
EP 0 626 640 and EP 0 626 641 disclose techniques for converting high level processing languages into machine language. These techniques require the intervention of a user to assess whether the value of an operation is likely to overflow when a program is executed by a computer. If so, a value correction operation is performed and may comprise a masking operation or a sign-extending operation depending on whether the operation is unsigned or signed.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided a method of translating a source operation on at least one source operand comprising a binary integer of a first bit-width to a corresponding target operation for evaluation by a processor which performs integer operations on binary integers of a second bit-width which is greater than the first bit-width, the method comprising: translating the source operation to a target operation having at least one target operand; identifying whether the value of unused bits of the or each target operand affects the value of the target operation and whether the target operand or any of the target operands is capable of having one or more unused bits of inappropriate value; and, if so, adding to the target operation a correcting operation for correcting the value of each of the one or more bits of inappropriate value before performing the target operation.
The at least one source operand may comprise at least one constant.
The at least one source operand may comprise at least one variable.
The at least one source operand may comprise at least one sub-operation.
The source operation may comprise an arithmetic operation. The identifying step may comprise identifying an unsigned unmasked target operand and the correcting step may comprise a ma
Kay Andrew
Zammit Vincent
Ingberg Todd
Nahar Qamrun
Renner , Otto, Boisselle & Sklar, LLP
Sharp Kabushiki Kaisha
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