Patent
1997-08-04
2000-04-18
Teska, Kevin J.
39550034, 3955004, G06F 1900
Patent
active
060525231
ABSTRACT:
Upon a transient analysis simulation, if a time step between calculation points is relatively small, a forced quit error occurs, which leads to deterioration of development efficiency. A voltage v.sub.n at a calculation point t.sub.n is obtained by solving a circuit equation. A change rate in the voltage v.sub.n in a step [t.sub.n-1, t.sub.n ] is assumed to be maintained in another step [t.sub.n, t.sub.n+1 ], and a calculation point t.sub.n+1 is temporarily determined so that v.sub.n+1 -v.sub.n is equal to a predetermined value .DELTA.v. The step t.sub.n+1 -t.sub.n is then judged if it falls within a dynamic range of a computer. If the step does not fall within the dynamic range, the calculation point t.sub.n is moved backward by a predetermined decrement, and the procedure is re-performed. If t.sub.n+1 -t.sub.n falls within the dynamic range, a voltage at the calculation point t.sub.n+1 is calculated.
REFERENCES:
patent: 5517585 (1996-05-01), Dowling
patent: 5566085 (1996-10-01), Marceau et al.
patent: 5758277 (1998-05-01), Hawkes
patent: 5799114 (1993-05-01), Dowling
List of Technical Memoranda, Technical Memoranda, Electronics Research Laboratory.
Choi Kyle J.
Mitsubshiki Denki Kabushiki Kaisha
Teska Kevin J.
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