Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-07-25
2004-05-04
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S684000, C438S107000, C438S118000
Reexamination Certificate
active
06730997
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a method of transferring ultra-thin substrates, in particular, semiconductor substrates including active devices as well as a multi-layer thin film device manufacturable using the transfer method.
TECHNICAL BACKGROUND
In order to try and increase density of packing of integrated circuits and semiconductor chips it is known to form a so called “cube” package consisting of a number of passivated device chips glued together in a stacked configuration. Conventionally these devices are connected via one of the side surfaces of the cube which is perpendicular to the layers of chips. One such known connection method is shown in
FIG. 1
which is described in EP 631 310. It includes a cube of glued chips
1
with connections on one of the sides of the cube which is perpendicular to the layers of chips. The side connection connects through to the output pins
3
of a carrier
2
. The cube is manufactured in the following way. Integrated circuit chips are formed on the upper surface of a wafer. Next a polymer adhesive material is applied to the top of the completed chips. The wafer is then diced and the plurality of integrated circuit chips are then stacked, one on top of another, using the adhesive to bond them together. The resulting cube structure is rather bulky as each layer of the stack includes both a chip and also a carrier (semiconductor wafer) for that chip.
A three-dimensional memory packaging is known from the article by Robert Bums, Warren Chase and Dean Frew, entitled “Utilising three-dimensional memory packaging and silicon on silicon technology for next generation recording devices”, ICMCM Proceedings 1992, pages 34 to 40. The known device is shown schematically in FIG.
2
and includes a 3D memory
5
connected by solder to the X and Y wiring or “routing”,
6
,
7
and the ground and source potential,
8
,
9
of an MCM substrate
10
which may be built up on a silicon substrate
11
. As with the device known from EP-631 310 the individual layers of the 3D memory
5
are stacked perpendicularly to the substrate
10
so that the complete assembly takes up quite a lot of space in the direction perpendicular to the substrate
10
.
A semiconductor package stack module is known from EP 729 184 in which a large scale integrated circuit (LSI) is mounted via fine bumps on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a three-dimensional stack module. This stack takes up quite a lot of room as each layer is relatively thick as it includes both a carrier layer and a chip. Further, the connections are made on one side of the cube resulting in the layers of chips being perpendicular to the substrate.
The above devices suffer from the problem that the cube packages are formed from relatively thick layers which not only makes them bulky but also negatively affects their thermal properties.
The handling of ultra-thin substrates, in particular semiconductor substrates such as semiconductor grade silicon, is difficult as such layers are brittle and are easily damaged. In addition the transfer of more than one layer to form a stack is particularly difficult as the previous transferred layer does not provide a perfectly flat base such that any attempt to transfer the next ultra-thin substrate may result in damage to this layer.
One method of transferring thin semiconductor substrates including active devices is described in U.S. Pat. No. 5,256,562. The method is not described in detail but it includes formation of thin film transistors on a first substrate. The transistor side of the substrate is then glued to a carrier substrate using an epoxy adhesive. The carrier may be glass. The first substrate would then appear to be removed although this step is not described and the carrier and the TFT's is transferred to a second substrate and adhered thereto with another adhesive (not specified). The glass carrier is then removed using hydrofluoric acid and the epoxy adhesive removed by oxygen plasma, sulphuric acid or boiling trichlorethylene. Alternatively, a removable epoxy is used to attach the glass carrier and this is removed by subjecting the epoxy adhesive to UV or microwave radiation, or chemicals (not specified) to destroy the adhesive properties of the epoxy layer. The epoxy layer is then removed by one of the methods described above. This known technique makes use of aggressive chemicals and complex procedures which means that the TFT's have to be protected by special layers. This makes the method inconvenient for commercial production. Further, no method is described of how to stack one layer of TFT's on another to form a three-dimensional structure of active devices. In fact, due to the use of aggressive chemicals the procedure is unsuitable for forming three-dimensional active structures.
AIMS OF THE INVENTION
It is an object of the present invention to provide a method of assembly of integrated circuit chips which allows the production of the stack of such chips with high density.
It is a further object of the present invention to provide a semiconductor device and a method of making the same which includes a three-dimensional structure of active and passive electronic devices which takes up less room than the known three-dimensional structures.
It is still a further object of the present invention to provide a method of safe transfer of very thin substrates, especially semiconductor substrates.
It is yet a further object of the present invention to provide a semiconductor device and a method of making the same having a three-dimensional structure of active and passive electronic devices which has better thermal and/or electrical properties than conventional devices.
SUMMARY OF THE INVENTION
The present invention may provide a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of: forming the first planar substrate; attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer; attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer; partly curing the polymer adhesive layer, and disconnecting the release layer from the first substrate to separate the first substrate from the carrier followed by curing the polymer adhesive layer.
The method may include the step of the curable adhesive being applied to the second substrate before the attaching step. The first substrate is preferably an ultra-thin semiconductor substrate formed by thinning a semiconductor substrate which is supported by the carrier and the release layer during the thinning operation. The semiconductor substrate may be provided with micro-trenches between dies which are formed on the surface to which the carrier is attached. The thinning of the semiconductor substrate should be continued until the trenches are reached. this results in an array of separated dies attached to the carrier by means of the release layer. By selective removal of these dies, the step of dicing the carrier can be avoided.
The present invention may also provide a multi-layer thin film device comprising: a plurality of layers, each layer including a planar three-dimensional interconnect portion having “X”, “Y” and “Z” connection routings and adjacent thereto a planar semiconductor device portion, the semiconductor device portion being connected to the interconnect portion in each layer, the “X” and “Y” routings lying in the plane of the interconnect portion and the “Z” routing being perpendicular thereto, the “Z” routing in each interconnect portion being selectably distributed throughout the interconnect portion. A Z connection through one layer may be located at a different position than a Z connection in either the layer above or below this one layer despite the fact that t
Beyne Eric
Coello-Vera Augustin
Vendier Olivier
Everhart Caridad
Imec VZW
Knobbe Martens Olson & Bear LLP
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