Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2000-03-14
2004-07-06
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
Reexamination Certificate
active
06760071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a control method of transferring charges. More specifically, it relates to a method of transferring charges for a CCD (Charge-Coupled Device) image-sensing device.
2. Description of the Related Art
CCD image-sensing devices are widely applied to image processing systems and digital signal processing systems, because they can serve as shift registers or sequential memory devices with high density. For example, CCD image-sensing devices are applied in scanners, digital cameras, copy machines, etc.
For conventional scanners or contact image scanners (CIS), their image processing portions comprise CCD image-sensing devices.
FIG. 1
shows a schematic structure of a CCD image-sensing device. In general, a CCD image-sensing device at least comprises: a row of image-sensing elements (P
1
~Pn) for sensing the light energy falling thereon and generating charge packets proportional to the light intensity; a CCD analog shift register with plural register elements (SH
1
~SH
2n
) for receiving and storing the charge packets in parallel; and an output amplifier (OP) for converting each of the charge packets into proportional voltage level (Vim). The CCD shift register is controlled by two clock signals &phgr;
1
and &phgr;
2
, shifting the charge packets stored in the register elements serially to the output amplifier (OP).
FIGS.
2
(
a
) to
2
(
f
) show the charge transferring process in the CCD shift register depicted in
FIG. 1
, and the waveforms of the clock signals &phgr;
1
and &phgr;
2
. The structure of the CCD shift register is schematically depicted in FIG.
2
(
a
). For brevity, only 5 gate electrodes (E
1
~E
5
) in the CCD shift register are shown, and the threshold voltage is 0. The 5 gate electrodes E
1
~E
5
and the p-type semiconductor substrate (hereinafter referred to as p-type substrate) P
sub
form 5 register elements.
At time t
1
, &phgr;
1
and &phgr;
2
are at voltage levels 0 and V. The distribution of potential barriers in the p-type substrate P
sub
is depicted as FIG.
2
(
b
). The potential barriers beneath the gate electrodes E
1
, E
3
, and E
5
are higher than those beneath the gate electrodes E
2
and E
4
. Hence, the charge packets (depicted as dash lines) will be stored in the regions beneath the gate electrodes E
2
and E
4
, in the p-type substrate P
sub
.
At time t
2
, both &phgr;
1
and &phgr;
2
are at voltage levels V/2, and the distribution of potential barriers in the p-type substrate P
sub
is depicted as FIG.
2
(
c
). The arrows depicted in FIG.
2
(
c
) mean when the time changes form t
2
to t
3
the potential barriers beneath odd electrodes will decrease and those beneath even electrodes will increase.
At time t
3
, &phgr;
1
and &phgr;
2
are at voltage levels 3V/4 and V/4, and the distribution of potential barriers in the p-type substrate P
sub
is depicted as FIG.
2
(
d
). Therefore, the charge packets stored beneath the gate electrodes E
2
and E
4
are transferred to the regions beneath the gate electrodes E
3
and E
5
with lower potential barriers.
Finally at time t
4
, &phgr;
1
and &phgr;
2
are at voltage levels V and 0, and the distribution of potential barriers in the p-type substrate P
sub
is depicted as FIG.
2
(
e
).
During the period from t
1
, to t
4
, the charge packets are transferred toward right side for an electrode. Similarly, during the periods from t
5
to t
6
and t
7
to t
8
, the charge packets are also transferred toward right side for an electrode.
The resolution of scanners generally is 600 dpi (dot/inch) or more, however, the resolution of 300 dpi is accurate enough for scanners to scan figures of texts and documents. For a scanner of 600 dpi resolution, the images in every inch of the scanned object are converted into 600 charge packets stored in a CCD shift register. Then, the 600 charge packets are shifted serially to the output amplifier for processing. However, even if the demanded resolution for processing is 300 dpi, the 600 charge packets still must be transferred out one by one. Consequently, the total processing speed is reduced.
For the scanner of 600 dpi resolution, if every two or more adjacent charge packets stored in the CCD shift register can be combined by adjusting the potential barrier distribution depicted in FIGS.
2
(
a
)~
2
(
e
), then only 300 or less adding (combined) charge packets stored in the CCD shift register must be transferred out to reconstruct the image of 300 dpi resolution, thereby improving the charge-transferring speed.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of transferring charge for a scanner.
The present invention achieves the above-indicated objects by providing a method of transferring charge for a CCD image-sensing device, the CCD image-sensing device at least having plural (y) image-sensing elements and a CCD shift register with plural (n=2y) register elements, each of the image-sensing elements operating in conjunction with two of the register elements, the method comprising the following steps.
Defining a specific number of the register elements (every k register elements) as a charge-combining portion, thereby providing plural (m) charge-combining portions.
Make the y image-sensing elements sense light energy falling thereon to generate y charge packets proportional to the light intensity.
Transfer the y charge packets in parallel to the CCD shift register; wherein the charge packets coupled to each of the m charge-combining portions is accumulated into one specific register element in each of the m charge-combining portions when the k register elements in each of the m charge-combining portions have coupled the charge packets from the image-sensing elements, thereby generating m adding charge packets in the m charge-combining portions.
Deliver each of the adding charge packets serially to the output of the CCD shift register and converting the adding charge packets into proportional voltage levels.
REFERENCES:
patent: 6069658 (2000-05-01), Watanabe
patent: 6275261 (2001-08-01), Yamazaki
patent: 6423959 (2002-07-01), Ikeda et al.
patent: 6452634 (2002-09-01), Ishigami et al.
patent: 6583818 (2003-06-01), Toma
Chen Michael
Wu Yung-Chuan
Avision Inc.
Garber Wendy R.
Tillery Rashawn N
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