Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2001-08-21
2003-02-25
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S460000, C438S622000, C156S230000, C156S241000
Reexamination Certificate
active
06524889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring pattern formation method, and an original substrate used for the method. More particularly, the present invention relates to a wiring pattern formation method manufactured at a wafer level, and an original substrate used for the method.
2. Description of the Related Art
Conventionally, a multiple-layer print wiring substrate having a plurality of wiring pattern layers sequentially transcribed onto a substrate and a method for manufacturing the same have been well known (refer to Japanese Laid Open Patent Application (JP-A-Heisei, 8-186375).
FIGS. 7A
,
7
B illustrate a wiring pattern formed on the conventional multiple-layer print wiring substrate.
FIG. 7A
is a sectional view showing the multiple-layer print wiring substrate, and
FIG. 7B
is a sectional view showing an original substrate for transcribing the wiring pattern. As shown in
FIGS. 7A
,
7
B, a multiple-layer print wiring substrate
1
has a plurality of wiring pattern layers
3
laminated on a substrate
2
(refer to FIG.
7
A).
This multiple-layer print wiring substrate
1
is manufactured by using a transcribing original substrate
4
. In the transcribing original substrate
4
, a wiring pattern layer
8
composed of a conductive layer
6
and an insulation resin layer
7
having an agglomerating property and an adhesive property is placed on a conductive substrate
5
in which at least surface has a conductive property (refer to FIG.
7
B).
When the multiple-layer print wiring substrate
1
is manufactured, a plurality of transcribing original substrates
4
is firstly produced. Then, this transcribing original substrate
4
is thermally pressed and adhere on one surface of the substrate
2
constituting the multiple-layer wiring pattern. Next, the conductive substrate
5
is removed from the substrate
2
, and the wiring pattern layer
8
is transcribed. After that, this transcribing operation is sequentially repeated, a plurality of wiring pattern layers
3
are laminated on the substrate
2
, and the multiple-layer print wiring substrate is manufactured.
However, a problem is induced when the wiring formation using the above conventional transcription is carried out in a wide area such as a wafer level. That is, when it is performed on the surface at the wafer state (the wafer level) without being done after the wafer is diced into individual chips, the sufficiently dimensional accuracy can not be obtained. Thus, it is impossible to apply the wiring formation using the conventional transcription. By the way, a method may be considered for again forming the wiring on the wafer by using a subtractive method or an additive method. However, in this case, it is impossible to avoid the manufacturing cost from being increased.
In short, in the case of the wiring formation using the conventional transcription, a metallic plate or an insulation substrate in which a conductive thin film is formed on a surface is used as the transcribing original substrate
4
. A difference of a linear expansion coefficient is not considered between the transcribing original substrate
4
and the substrate
2
. Moreover, the transcription to the substrate
2
of the wiring pattern is done by the thermally pressing adhesive operation under the condition at a temperature from 180 to 200° C. and a pressure from 40 to 50 kgf/cm
2
.
For this reason, if the wiring formation using the conventional transcription is diverted to the wiring formation at the wafer level, a large dimensional error is induced in the transcribed wiring pattern, since the transcription target has the wide area at the wafer level, in addition to the difference of the linear expansion coefficient between the transcribing original substrate and the wafer.
For example, if an original substrate made of stainless steel is used to transcribe a wiring pattern at a temperature of 200° C. onto a wafer having a diameter of about 300 mm, the difference of the linear expansion coefficient causes a dimensional error of about 300 &mgr;m to be induced at both ends of the wafer. Here, the linear expansion coefficient of the original substrate made of stainless steel is 16 ppm/degree, and the linear expansion coefficient of the wafer is 4 ppm/degree.
In order to cope with such a dimensional error, a dimensional correction may be often done for considering the difference of the linear expansion coefficient. However, in this case, the value of the dimensional correction must be changed if the temperature in the pressing and adhering operation at the time of the transcription is different.
Also, when the wiring layer is formed on the wafer, the subtractive method and the additive method are mainly used. Here, the subtractive method sticks a metallic foil on a wafer and then forms a pattern by using an etching operation. The additive method forms a wiring pattern by using a metallic plating operation.
With regard to both the methods, the subtractive method is high in technical perfectivity and low in cost. However, it is not suitable for the formation of micro pattern. On the contrary, the additive method is suitable for the formation of micro pattern. However, it is high in cost and lack of reliability.
Moreover, if the multiple-layer wiring is formed, the procedure is repeated in turn for forming the insulation layer after the wiring pattern layer is formed by using the above-mentioned method. However, the occurrence of a trouble in an interlayer causes a manufacturing cost to be increased since the repairing of a product is difficult.
It is therefore an object of the present invention to provide a wiring pattern formation method, which can obtain a sufficiently dimensional accuracy even if the wiring formation using the transcription is carried out in the wide area such as the wafer level and can also avoid a manufacturing cost to be increased, and an original substrate used for the method.
SUMMARY OF THE INVENTION
In order to attain the above-mentioned object, a wiring pattern formation method according to the present invention is characterized in that a wiring pattern formation method, which forms a wiring pattern on a substrate through a transcribing operation, includes a transcribing step of thermally pressing and adhering on the substrate the transcribing original substrate that contains a wiring layer to be transcribed and has a linear expansion coefficient in which a dimensional error from the substrate is within a predetermined range in a heated condition, and then adhering and transcribing the wiring layer.
Due to the above-mentioned configuration, the transcribing original substrate that contains the wiring layer to be transcribed and has the linear expansion coefficient in which the dimensional error from the substrate is within the predetermined range in the heated condition is thermally pressed and adhered on the substrate, and the wiring layer is adhered and transcribed, and the wiring pattern is formed on the substrate through the transcribing operation. Thus, even if the wiring formation using the transcription is carried out in the wide area such as the wafer level, it is possible to obtain the sufficiently dimensional accuracy and further possible to avoid the manufacturing cost to be increased.
Also, the original substrate used for the wiring pattern formation method according to the present invention enables the wiring pattern formation method to be attained.
REFERENCES:
patent: 5151388 (1992-09-01), Bakhit et al.
patent: 5192716 (1993-03-01), Jacobs
patent: 5258236 (1993-11-01), Arjavalingam et al.
patent: 5691245 (1997-11-01), Bakhit et al.
patent: 6036809 (2000-03-01), Kelly et al.
patent: 6294407 (2001-09-01), Jacobs
patent: 3-270292 (1991-12-01), None
patent: 8-186375 (1996-07-01), None
“Low Expansion Block for Chip Carrier,” IBM Technical Disclosure Bulletin v. 21 No. 3 p. 951, Aug. 1978.*
“Process for Direct Printing of High-Resolution Metal Patterns,” IBM Technical Disclosure Bulletin v. 32 No. 3A pp. 465-467, Aug. 1989.*
C. Narayan et al., “Thin Film Transfer
NEC Corporation
Smoot Stephen W.
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