Method of topography management in semiconductor formation

Details Method of topography management in semiconductor formation Method of topography management in semiconductor formation

2002-01-18

2003-05-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S425000, C438S426000, C257S510000

Reexamination Certificate

active

06559028

ABSTRACT:

FIELD OF THE DISCLOSURE
The present invention relates generally to a semiconductor manufacturing process, and more particularly to a method for management of topography in formation of a device having shallow trench isolation features.
BACKGROUND
Isolation of a semiconductor device is generally achieved by utilizing local oxidation of silicon (LOCOS) or shallow trench isolation (STI) techniques. LOCOS is a low cost, uncomplicated manufacturing process, however, the higher packing density requirements of very large scale integration (VLSI) or ultra large scale integration (ULSI) limit the application of LOCOS technology. In STI device isolation techniques, isolation is provided by forming a recess or trench between two active areas, and filling the trench with an isolation material. STI serves to provide higher packing density, improved isolation, and greater planarity by avoiding at least some of the topographical irregularities associated with LOCOS.
When creating the STI structure, it is desirable for the uppermost surface of the substrate to be as coplanar (i.e., flush) as possible with the uppermost surface of the trench fill. This coplanarity maximizes the performance of the finished device, and provides a flat topography for ensuing processing. However, substantial planarity is difficult to achieve in current practices. For example, the use of a thick nitride layer as a combination patterning layer and polish stop results in the undesirable formation of a large step. Such a topographical step makes it difficult to photolithographically process subsequent layers of the device with accuracy, particularly in forming submicron features, thus adversely impacting process yield and production costs. This problem is heightened as circuit geometry is reduced to 0.250 microns and below.
Unfortunately, the thickness of the nitride layer, typically about 1600 to 1800 angstroms, cannot be reduced to the point necessary for it to function effectively as a polish stop (typically between about 300 to 1000 angstroms, depending upon variables in the polishing process) because its thickness is optimized for photolithographic processing. Accurate photolithographic processing requires that the nitride layer on which the mask is formed have a specific optical reflectivity which, in turn, requires the nitride layer to have a thickness greater than that desired for it to function as a polish stop. Furthermore, any change in the thickness of the nitride layer must be made in quantum increments, e.g., 400 angstroms either thicker or thinner at a time, due to the nature of its optical properties. Hence it is difficult to optimize the thickness of the nitride layer as to its polish stop function without adversely impacting subsequent photolithographic processing.
Thus there exists a continuing need for a method of manufacturing a semiconductor device which enables further reduction in the topographical step between the uppermost surface of the substrate or epitaxial layer and the uppermost surface of the trench, without adversely affecting photolithographic processing of the source/drain mask.


REFERENCES:
patent: 5930645 (1999-07-01), Lyons et al.
patent: 6403483 (2002-06-01), Hao et al.

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