Method of timing sampling frequency pulses for digitizing and st

Details Method of timing sampling frequency pulses for digitizing and st Method of timing sampling frequency pulses for digitizing and st

1986-10-01

1988-06-14

Britton, Howard W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358150, 358319, H04N 506

Patent

active

047515759

ABSTRACT:
A highly stable clock pulse frequency (f2), which may be locked to a central clock pulse source of a broadcasting studio, is used to clock digital color television signals out of a buffer memory (1) and is also frequency multiplied by a factor (n). The output of the frequency multiplier (10) is divided by the same factor (n) in a synchronous divider (11) which counts out every nth pulse and to which horizontal synchronization pulses derived from tape recorded television signals are supplied at a reset input of the synchronous divider. The output (f1=f3
) of the synchronous divider is used both for clocking the analog to digital converter which converts the color television signals picked up from the tape into digital signals and for clocking the entry of those digital signals into the buffer memory (1). Resetting of the divider by horizontal synchronizing pulses containing the same timing errors as the digital signals put into the buffer memory, causes the divider to begin a fresh counting cycle on the next positive flank of a frequency-multiplied clock pulse (f3), thus correcting the timing errors except for a possible residual timing error which is less than the oscillation period of the frequency multiplied clock pulses, which can be made smaller by using a higher multiplication and division factor (n).

REFERENCES:
patent: 4215376 (1980-07-01), Mach
patent: 4392159 (1986-07-01), Lemoine et al.

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