Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2009-05-29
2011-10-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S134000
Reexamination Certificate
active
08046724
ABSTRACT:
Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.
REFERENCES:
patent: 7458049 (2008-11-01), Tuncer et al.
patent: 2009/0288051 (2009-11-01), Hemmett et al.
“Statistical Timing Optimization of VLSI Circuits under Process Variation” (Park, Hyun-Soo, Doctoral Degree Thesis, Invention Disclosed in pp. 91-114 (Nov. 11, 2008)).
Korean Intellectual Property Office, Non-final Rejection, Application No. 10-2009-0024083, dated Dec. 22, 2010.
Ihyoun Soo Park, Wook Kim, Dai Joon Hyun and Young Hwan Kim, Timing Criticality for Timing Yield Optimization, IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2008, pp. 3497-3505, vol. e91-A, No. 12.
Hyun Dai Joon
Kim Wook
Kim Young Hwan
Park Hyoun Soo
Kile Park Goekjian Reed & McManus PLLC
Lee Eric
Postech Academy-Industry Foundation
Siek Vuthe
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