Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
2001-05-23
2004-12-21
Le, Amanda T. (Department: 2634)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S150000
Reexamination Certificate
active
06834074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to data communication systems and methods, and more particularly to method of time tracking in a vector correlator based Rake receiver.
2. Description of the Prior Art
Conventional Rake receivers employ chip by chip correlation techniques in which each chip is multiplied by a PN as it arrives, and the results are summed together. Although such techniques are effective, more flexibility can be obtained using vector correlation in which a plurality of chips are simultaneously multiplied by a plurality of PNs prior to summing the results. Such vector correlation can provide enhanced flexibility for example, by allowing implementation of a central data path having many fingers that can be efficiently processed. A system that employs a vector correlator based Rake receiver is disclosed in '410 and '184 U.S. patent applications referenced herein above. That system employs a circular buffer (triple data buffer) to receive incoming streams of data. Unlike time tracking techniques associated with conventional Rake receivers, time tracking techniques used with any system that employs a vector correlator must also address boundary effects due to the fixed vector of data samples available.
In view of the foregoing, it is therefore desirable to provide a method of time tracking in a system such as a vector correlator based Rake receiver that employs a circular buffer.
SUMMARY OF THE INVENTION
The present invention is directed to a method of time tracking in a system such as a vector correlator based Rake receiver that employs a circular buffer. According to one embodiment, a method of time tracking in a vector correlator based Rake receiver having a 48-chip triple data input buffer, resolves a timing change associated with a particular multipath by processing twice the number of chips that are normally processed when the earliest chips in the input buffer are to be processed and time tracking needs to be implemented with an earlier sample, and further, by idling one extra cycle to prevent chip processing for a particular cycle when the chips being processed are the latest 16-chips in the 48-chip triple data input buffer and time tracking needs to be implemented with a later sample before tracking to the earliest 16-chips in the input buffer. A predetermined software algorithm directs specific hardware to track early, ontime, or late; and the hardware determines if the earliest or latest chips in the input buffer need to be processed.
According to one embodiment, a method of time tracking in a vector correlator comprises the steps of:
providing a vector correlator based system having a triple data input buffer wherein two of three buffers are available for processing by a correlator datapath while the remaining buffer is being written into by incoming chips, and further wherein one of the two buffers of the triple data input buffer contains a plurality of early sets of chips (16 in one embodiment) while the remaining buffer contains a plurality (again 16 in one embodiment) of temporally late sets of chips;
receiving chip samples into the triple data input buffer;
despreading a plurality of triple data input buffer chips (16 in one embodiment) selected from the two buffers available for processing by the correlator datapath, in a single correlation processing cycle;
detecting a timing change associated with the chip samples through commands transmitted to the vector correlator from a host processor;
detecting a first event where a timing change to an earlier sample is commanded by the host processor while the current chips being processed are the earliest in the triple data input buffer, and the sample being processed is the earliest sample;
despreading the latest samples of chips from the latest third within the triple data input buffer upon completion of the timing change command by the host processor (necessary to affect the timing change when the earlier chip sample falls outside of the earliest third of the triple data input buffer that was being processed before the timing change command);
despreading via parallel processing the earliest third of the triple data input buffer chips in the same correlation processing cycle as the latest third of the triple data input buffer chips (parallel processing necessary to ensure processing of incoming chips is not skipped);
detecting a second event where a timing change to a later sample is commanded by the host processor while the current chips being processed are the latest in the triple data input buffer, and the sample being processed is the latest sample;
skipping one correlation cycle upon the occurrence of the second event; and
despreading the earliest sample of each chip associated with the earliest set of chips in the triple data input buffer upon completion of the timing change command by the host processor and subsequent to the skipped correlation cycle (necessary to prevent processing of the same set of chips twice).
According to another embodiment of the invention, a method of time tracking in a vector correlator, comprises the steps of:
providing a vector correlator based Rake receiver having a triple data input buffer having two of three buffers available for processing by a correlator datapath while the remaining buffer is being written into by incoming chips, and further wherein one of the two buffers of the triple data input buffer available for processing contains a plurality of early sets of chips (16 in one embodiment) while the remaining buffer contains a plurality (again 16 in one embodiment) of temporally late sets of chips;
receiving chip samples into the triple data input buffer;
detecting early, ontime and late timing changes associated with the received chip samples via commands transmitted to the Rake receiver from a host processor;
despreading a plurality of triple data input buffer chips (16 according to one embodiment) selected from the two buffers available for processing by the correlator datapath, in a single correlation cycle;
despreading a plurality of the earliest third of the triple data input buffer chips and a plurality of the latest third of the triple data input buffer chips in a single correlation processing cycle subsequent to wrapping the earliest set of chip samples back into the latest triple data input buffer portion such that latest triple data input buffer chips can be processed in response to the timing change to implement time tracking in subsequent processing cycles; and
skipping one correlation processing cycle when the latest triple data input buffer chips are to be processed and the timing change indicates time tracking needs to be done to a later chip sample that falls outside the latest third of the triple data input buffer chip portion.
In one aspect of the invention, a method of time tracking for a system having a triple data input buffer allows demodulation of a particular multipath at a particular timing condition, even when the multipath is not constant (shifting).
In another aspect of the invention, a method of time tracking for a system having a triple data input buffer allows demodulation of a particular multipath even when the earliest available chips in the input buffer must be processed and time tracking needs to be done to an earlier sample.
In yet another aspect of the invention, a method of time tracking for a system having a triple data input buffer allows demodulation of a particular multipath even when the last available chips in the input buffer must be processed and time tracking needs to be done to a later sample.
REFERENCES:
patent: 5654979 (1997-08-01), Levin et al.
patent: 5867527 (1999-02-01), Ziv et al.
Brown Katherine G.
Lee Yuan Kang
Sriram Sundararajan
Brady III Wade James
Le Amanda T.
Neerings Ronald O.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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