Method of thinning for EEPROM tunneling oxide device

Details Method of thinning for EEPROM tunneling oxide device Method of thinning for EEPROM tunneling oxide device

1994-09-14

1995-08-08

Fourson, George

Fishing, trapping, and vermin destroying

437 52, 437984, 257316, 257326, H01L 21266, H01L 218247

Patent

active

054398380

ABSTRACT:
A method of forming an EEPROM memory cell on a semiconductor substrate, comprises forming a first dielectric layer on the substrate, a gate electrode of a select transistor and a first layer of a floating gate electrode of an EEPROM device on the dielectric layer, ion implanted source/drain regions in the substrate adjacent to the gate electrode and the first layer of the floating gate electrode proximate to at least the periphery of the gate electrode and the first layer of the floating gate electrode. The central region of the ion implanted regions is between the gate electrode and the first layer of the floating gate electrode. A tunneling oxide layer is formed above the central region using the electrodes to form the boundaries of the tunneling oxide layer, a second layer of the floating gate electrode in contact with the first layer of the floating gate electrode and in contact with the upper surface of the tunneling oxide layer, additional dielectric material over the upper surface of the device, and a control gate electrode deposited upon the surface of the additional dielectric material.

REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5067108 (1991-11-01), Jeng
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5153144 (1992-10-01), Komori et al.
patent: 5225362 (1993-07-01), Bergemont
patent: 5352620 (1994-10-01), Komori et al.

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