Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-04-01
2001-05-22
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06236225
ABSTRACT:
TECHNICAL FIELD
The invention relates to a method of testing the gate oxide in integrated DMOS power transistors and an integrated device comprising a DMOS power transistor.
BACKGROUND OF THE INVENTION
As is known, it is desirable to be able to test and “screen” DMOS power transistors in the inspection phase by applying a stress to the gate oxide of the transistors for the purpose of reducing their failures during their operational life, by eliminating the weakest components in the inspection phase.
Furthermore, to perform validity tests in integrated power circuits, it is known to equip such circuits with dedicated contact pads to which stress voltages suitable for testing power components are applied; this technique cannot, however, be: used directly for DMOS transistors in that the high voltages that are necessary to stress the gate oxide of such components sufficiently (30 V for example) are not compatible with the control circuitry and could lead to breakage.
On the other hand, in some applications such as the motor vehicle field, it is desired to guarantee failures of operating devices tending towards 0 p.p.m. and it thus becomes increasingly necessary to have methods of test for DMOS power transistors.
SUMMARY OF THE INVENTION
An object of the invention is therefore to provide an inspection method which enables DMOS power transistors to be tested without damaging the other components of the integrated circuit.
In accordance with a method of the present invention, the gate oxide of an integrated DMOS power transistor having a gate terminal connected to a control element comprises the steps of arranging a switch element between the control element and the gate terminal of the DMOS power transistor; maintaining the switch element in an open condition; applying a stress voltage to the gate terminal; and testing the DMOS power transistor through a test condition. In another aspect of the present invention, the method includes the further step of short-circuiting the switch element that is carried out in the event the test condition is passed.
In accordance with another aspect of the present invention, the switch element comprises an electronic switch device equipped with a normally-open control terminal, and the step of maintaining the switch element comprises leaving the normally-open control terminal floating.
In accordance with a further aspect of the method of the present invention, the electronic switch device comprises a first terminal connected to the gate terminal of the DMOS power transistor and a second terminal connected to the control element, and the step of applying a stress voltage comprises the step of applying a first voltage drop between the first and second terminal with the first voltage drop having a value lower than a breakdown voltage of the electronic switch device.
In accordance with still yet another aspect of the present invention, a method of testing gate oxide of an integrated DMOS power transistor having a gates terminal and a control element is provided. The method comprises the following steps: Forming an integrated switch element between the control element and the gate terminal with at least a first terminal connected to the control element and a second terminal connected to the gate terminal; forming a normally-open fusible link across the first and second terminals of the switch element; applying a stress voltage to the gate terminal of the DMOS power transistor while maintaining the switch element in an open condition, and testing the gate oxide of the DMOS power transistor through a test condition. In accordance with another aspect of the present invention, the method comprises the further step of applying a fusion current to the fusible link to cause at least a partial fusion together of the fusible link and thereby electrically shorting the first and second terminals of the switch element and electrically connecting the control element to the gate terminal. Ideally, the step of applying a stress voltage comprises applying a first voltage drop between the first and second terminals of the switch element of a value lower than the breakdown voltage of the switch element.
In accordance with still yet a further aspect of the present invention, an integrated circuit device is provided that comprises: a DMOS power transistor having a gate terminal; a control element having at least one output; a normally-open switch element having at least first and second terminals, with the first terminal connected to the gate terminal and the second terminal connected to the output terminal of the control element for electrically isolating the control element from the DMOS power transistor; and a normally-open fusible link formed across the first and second terminals.
In accordance with a further aspect of the present invention, the fusible link includes a first conductive element connected to the first terminal of the switch element and a second conductive element connected to the second terminal of the switch element, and an insulating region between the first and second conductive elements. The switch element comprises a bipolar junction transistor having base, emitter, and collector terminals, with the base terminal being floating, the collector terminal connected to the first terminal of the switch element, and the emitter terminal connected to the second terminal of the switch element.
REFERENCES:
patent: 5287055 (1994-02-01), Cini et al.
patent: 5381105 (1995-01-01), Phillips
patent: 5502399 (1996-03-01), Imai
patent: 5654863 (1997-08-01), Davies
patent: 5770947 (1998-06-01), Brauchle
patent: 5917319 (1999-06-01), Frank
patent: 4426307 A1 (1996-02-01), None
patent: 0 669 537 A1 (1995-08-01), None
patent: WO 95/10785 (1995-04-01), None
Bertotti Franco
Murari Bruno
Novarini Enrico
Galanthay Theodore E.
Kerveros J
Metjahic Safet
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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