Method of testing switches and switching circuit

Details Method of testing switches and switching circuit Method of testing switches and switching circuit

1992-05-28

1994-09-13

Chin, Wellington

Communications: electrical

Continuously variable indicating

With meter reading

371 204, 379 10, 379 15, H04L 1226, H04M 326

Patent

active

053472705

ABSTRACT:
Incoming lines (I0 to I7) are connected to a space switch (2) through input data latches (1). The space switch (2) is connected to a normal/test changeover switch (12), which is connected to a normal/test changeover switch (13) through serial-to-parallel converting circuits (3), common buffer memories (4) and parallel-to-serial converting circuits (5). Space switches (6) are connected to the normal/test changeover switch (13). Outgoing lines (O0 to O7) are connected to the space switches 6 through output data latches (8). Connection states in the switches (2, 6) are placed in transposed relation to each other by a transposed connection generating circuit (10) in a test operation, so that the switches (2, 6) are directly connected to each other through the switches (12, 13). Predetermined data applied to the incoming lines are intactly used as expected values for judgement of the normal or abnormal operation of the set of switches of matrix structure.

REFERENCES:
patent: 3618015 (1971-11-01), Homonick
patent: 3851122 (1974-11-01), Gibson
patent: 5142652 (1992-08-01), Schefts
ISSCC '91 Digest of Technical Papers, pp. 242-243, and p. 321, Japan "A 400Mb/s 8.times.8 BiCMOS ATM Switch LSI with 128kb On-Chip Shared Memory", S. Tanaka, et al.

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