Method of testing semiconductor device

Details Method of testing semiconductor device Method of testing semiconductor device

2002-10-17

2003-11-18

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S754120, C250S310000, C250S492200

Reexamination Certificate

active

06650129

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of testing a semiconductor device. More particularly, the invention relates to a method of testing a semiconductor device which measures characterizing dimensions such as a via covering amount, a misalignment amount and a short margin in the course of the manufacture of the semiconductor device.
2. Description of the Background Art
Conventionally, tests have been conducted as appropriate on semiconductor devices in the course of the manufacture of the semiconductor devices for the purpose of maintaining the quality of products or detecting manufacturing failures in an early stage. An example of the methods of such tests includes measuring a connection (a via covering amount) of an upper-level interconnect line to a via plug, a short margin between interconnect lines and the like, which exhibit variations particularly in the course of manufacture. This method employs a scanning electron microscope (SEM) and an overlay measurement apparatus using an optical technique in combination.
A background art method of testing a semiconductor device for poor connection of an upper-level interconnect line to a via plug is described.
FIG. 23
is a sectional view showing the design of a semiconductor device.
FIG. 24
is a sectional view of a semiconductor device actually manufactured based on the design of FIG.
23
.
In
FIGS. 23 and 24
, the reference numeral
1
designates a lower-level interconnect line;
2
designates an interlayer insulation film;
4
designates an upper-level interconnect line; and
3
designates a via plug for electrical connection between the lower-level interconnect line
1
and the upper-level interconnect line
4
. Reference character a designates a via covering amount; b designates a via plug diameter; c designates an upper-level interconnect line width; b′ designates the design value of the via plug diameter; a′ designates the design value of the via covering amount; c′ designates the design value of the upper-level interconnect line width; d′ designates the design value of a misalignment amount (or a distance between the center of the via plug diameter b′ and the center of the upper-level interconnect line width c′); and d is a misalignment amount, that is, the amount of misalignment from the design value d′ which occurs during actual pattern formation. Thus, d+d′ is an actually formed distance between the center of the via plug diameter b and the center of the upper-level interconnect line width c.
The via covering amount a′ is defined during the design phase in a manner to be described below. The end of the upper-level interconnect line
4
which is closer to the central axis of the via plug
3
is referred to as a first end, and the end of the via plug
3
on the opposite side from the first end is referred to as a second end. Then, the via covering amount a′ is a distance between the first end and the second end (See FIG.
23
).
The via covering amount a is a distance between the first and second ends defined when the above-mentioned design is prepared (See FIG.
24
).
A conventional method of examining the via covering amount a of the upper-level interconnect line
4
with respect to the via plug
3
is described with reference to
FIGS. 23 and 24
.
Referring to
FIG. 23
, the via covering amount a′ of the upper-level interconnect line
4
with respect to the via plug
3
is given by
a
′=(
b′+c
′)/2
−d
′  (1)
On the other hand, with reference to
FIG. 24
, the via covering amount a of the upper-level interconnect line
4
with respect to the via plug
3
is similarly given by
a
=(
b+c
)/2−(
d′+d
)  (2)
Subtracting Equation (1) from Equation (2) provides
a=a
′+(
b−b
′)/2+(
c−c
′)/2
±d
  (3)
which is an equation for the via covering amount a when the semiconductor device is actually manufactured. In Equation (3), the sign in front of “d” is “minus” when the center of the actually formed upper-level interconnect line
4
is misaligned leftwardly from the center of the upper-level interconnect line
4
in the design phase, and is “plus” when it is misaligned rightwardly.
Thus, the via covering amount a of the upper-level interconnect line
4
with respect to the via plug
3
is determined indirectly from Equation (3) by measuring the via plug diameter b and the upper-level interconnect line width c by means of the SEM and measuring the misalignment amount d by means of the overlay measurement apparatus using the optical technique.
In this manner, the background art method has measured the via cover amount a to test for poor connection of the upper-level interconnect line to the via plug.
A background art test for a failure between adjacent interconnect lines has been conducted by directly measuring a short margin between adjacent upper-level interconnect lines
4
by means of the SEM.
However, the overlay measurement apparatus employing the optical technique for use in determination of the via covering amount a is not capable of reducing errors to a negligible level due to the performance thereof to fail to measure the via covering amount a with high accuracy because of the errors. Therefore, the overlay measurement apparatus is not capable of conducting a test for poor connection of the upper-level interconnect line
4
to the via plug
3
accurately.
Measuring the short margin between the upper-level interconnect lines
4
presents no problem if the upper-level interconnect lines
4
have a uniform width as shown in FIG.
25
. In actual manufacture, however, the upper-level interconnect lines
4
have a taper (or inclination) as shown in FIG.
26
. Specifically, the upper-level interconnect lines
4
have a bottom width c
2
greater than a top width c
1
. If the upper-level interconnect lines
4
have the above-mentioned taper and a high aspect ratio, the above-mentioned SEM testing method is not capable of observing the bottom width c
2
.
In a damascene structure shown in
FIG. 27
, the bottom of the upper-level interconnect lines
4
is formed inside the interlayer insulation film
2
. Thus, the above-mentioned SEM testing method also is not capable of observing the bottom width c
2
.
In the instances shown in
FIGS. 26 and 27
, the testing method for failure between the upper-level interconnect lines
4
is not capable of measuring the short margin between the upper-level interconnect lines
4
with high accuracy to find it difficult to conduct a test for failure between the interconnect lines accurately.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of testing a semiconductor device which is capable of accurately measuring a via covering amount of an upper-level interconnect line with respect to a via plug, a short margin between (upper-level) interconnect lines and the like which exhibit process variations.
The present invention is intended for a method of testing a semiconductor device being manufactured on a semiconductor substrate by detecting secondary electrons produced by irradiation of a predetermined region with a primary electron beam and using a voltage contrast produced based on the intensity of the secondary electrons. According to the present invention, the method includes the following steps (a) through (h). The step (a) is to prepare a predetermined pattern to be tested. The step (b) is to prepare a reference pattern similar in construction to the predetermined pattern. The step (c) is to produce the voltage contrast of the predetermined pattern. The step (d) is to produce the voltage contrast of the reference pattern. The step (e) is to make a comparison between the voltage contrast of the predetermined pattern and the voltage contrast of the reference pattern to produce a first comparison image, and to binarize the first comparison image. The step (f) is to produce a second comp

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