Method of testing phase lock loop status during a...

Details Method of testing phase lock loop status during a... Method of testing phase lock loop status during a...

2006-12-05

2006-12-05

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S108000

Reexamination Certificate

active

07146284

ABSTRACT:
System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test (BIST). An existing pseudo random binary sequence (PRBS) data generator is modified to include a mode that produces a data pattern having a frequency content low enough to be verified on the tester used at the probe.

REFERENCES:
patent: 6201829 (2001-03-01), Schneider
patent: 6834367 (2004-12-01), Bonneau et al.
Newell, J.C.; “High speed pseudo-random binary sequence generation for testing and data scrambling in gigabit optical transmission systems”; IEE Colloquium on Gigabit Logic Circuits; Apr. 3, 1992; pp. 1/1-1/4.
Hetherington, G; Simpson, R; “Circular Bist Testing The Digital Logic With A High Speed Serdes”; Proceedings International Test Conference, 2003; vol. 1; Sep. 30-Oct. 2, 2003; pp. 1221-1228.

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