Method of testing networks on a wafer having grounding points on

Electricity: measuring and testing – Plural – automatically sequential tests

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324 62, G01R 3102, G01R 2702, G01R 3128

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active

044867050

ABSTRACT:
Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1, is a network 11'0 interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

REFERENCES:
patent: 3803483 (1974-04-01), McMahon
patent: 3808527 (1974-04-01), Thomas
patent: 3974443 (1976-08-01), Thomas
patent: 4220917 (1980-09-01), McMahon
Freed, L. E., "Test Circuit Configuration for Integrated Circuits" IBM Technical Disclosure Bulletin; vol. 14, No. 5, Oct. 1971, pp. 1598-1599.
Klein et al., "Chip Power Test Circuit" IBM Tech. Discl. Bulletin; vol. 22, No. 8A, Jan. 1980, pp. 3256-3257.

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