Method of testing n-bit programmable counters

Details Method of testing n-bit programmable counters Method of testing n-bit programmable counters

1990-01-03

1991-02-05

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Identifying or correcting improper counter operation

365201, 371 24, H03K 2140

Patent

active

049911856

ABSTRACT:
This invention relates to a method of testing an n-bit programmable counter. It is desired to test the n-bit programmable counter in fewer than 2.sup.n cycles. Accordingly, a counter value output on the counter is coupled to a variable increment rate input on the counter. Each bit of the counter is reset to a binary 0 initial state. A binary 1 state is loaded into a carry-in bit of the counter and the counter is iteratively doubled, by means of the coupling between the counter value output and the variable increment rate input, until a carry-out bit of the counter assumes the binary 1 state to thereby allow the counter to be fully tested in n+1 iterations. The counter value output and the variable increment rate input are decoupled from the counter when the counter is not being tested. The counter is provided with a parallel load input to allow simultaneous resetting of each bit. Intermediate counter values may be checked to provide a means for localizing errors within the counter.

REFERENCES:
patent: 4661930 (1987-04-01), Tran
patent: 4757523 (1988-07-01), Tran
patent: 4860325 (1989-08-01), Aria et al.

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