Method of testing integrated circuits

Details Method of testing integrated circuits Method of testing integrated circuits

1999-11-22

2002-09-03

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S760020

Reexamination Certificate

active

06445205

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to a method of testing an integrated circuit, in particular an integrated circuit having an internal bus which is not observable on the pins of the circuit. An example of this is a chip with a Harvard architecture.
BACKGROUND OF THE INVENTION
In the manufacture of ASICs (Application-Specific Integrated Circuits), it is particularly advantageous to be able to test the circuits before they are mounted in a product, because of the extra costs which arise if a circuit is found at that late stage to be faulty.
A particular problem in testing ASICs is that it is often desirable to monitor signals on an internal bus as part of the test. However, there may be no way of monitoring signals which are carried on this bus. This is of particular concern when the system has an internal processor, and it is desired to monitor signals passed between the processor and memories or other circuit blocks. For example, in the case of a Harvard architecture chip, in which the central processor has an address bus and a data bus for the program, and an address bus and a data bus for data, the program buses are typically connected to an external memory, and used for reading instructions to the processor. Since this bus goes to an external device, it is possible to monitor signals which are passed on the bus. However, the data buses typically stay on-chip, which means that there will be no way to monitor the activity on these buses, unless special measures are taken.
JP-63-133234 discloses a microcomputer, having a data bus and an address bus, provided with an on-chip device for carrying out a test.
In particular, this device includes a CRC arithmetic register, which may typically be in the form of a linear feedback shift register, which is set into an initial operational state, before the test is carried out. During the test, data on the bus which is studied are used to calculate a checksum, which after the test, can be read out.
The use of a CRC-register in the form of a shift resister with feedback can cause problems in the event that an “undefined” signal enters the shift register. The feedback means that, eventually, undefined bits can fill the register.
Moreover, the process of storing the data during the complete test, and subsequently reading the data, means that no error can be detected until the test is complete.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the invention, an integrated circuit includes a linear shift register without feedback, which converts signals on a bus into a serial bitstream. The integrated circuit has an output pin connected to the linear shift register to receive the serial bitstream thereon.
This has the advantage that the signals on the bus under investigation can be monitored continually throughout the test. In the event that a fault is discovered, the test can be terminated much more quickly than when using a device which requires the test to be completed before any data can be read out.
Moreover, the absence of feedback means that the presence of an undefined bit in the register will persist only for a limited number of clock cycles.
In accordance with a second aspect of the invention, there is disclosed a method of testing an integrated circuit, in which signals on a bus are converted into a bitstream, and read during the test from an output pin of the integrated circuit, and are then compared in a test device with an expected bitstream.
Again, this has the advantage that, as soon as a device is determined to be faulty, the test can be terminated without wasting further time.


REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 4467420 (1984-08-01), Murakami et al.
patent: 4498172 (1985-02-01), Bhavsar
patent: 4683569 (1987-07-01), Rubin
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 4878168 (1989-10-01), Johnson et al.
patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 4885538 (1989-12-01), Hoenniger III et al.
patent: 4897818 (1990-01-01), Redwine et al.
patent: 4967142 (1990-10-01), Sauerwald et al.
patent: 5153882 (1992-10-01), Lyon et al.
patent: 5253255 (1993-10-01), Carbine
patent: 5301199 (1994-04-01), Ikenaga et al.
patent: 5331571 (1994-07-01), Aronoff et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5428625 (1995-06-01), Dekker
patent: 5428770 (1995-06-01), Garner
patent: 5515382 (1996-05-01), Lassorie
patent: 5809036 (1998-09-01), Champlin
patent: 5892961 (1999-04-01), Trimberger
patent: 6035380 (2000-03-01), Shelton et al.
patent: 6101457 (2000-08-01), Barch et al.
patent: 60189545 (1985-09-01), None
patent: 62055955 (1987-03-01), None
patent: 63133234 (1988-06-01), None
patent: 63286780 (1988-11-01), None
patent: 1221686 (1989-09-01), None
patent: 4033134 (1992-02-01), None
patent: 4050784 (1992-02-01), None
patent: 4070933 (1992-03-01), None
patent: 4289473 (1992-10-01), None
patent: 4294430 (1992-10-01), None
patent: 5249183 (1993-09-01), None
patent: 6201782 (1994-07-01), None
patent: 7151828 (1995-06-01), None
patent: 7271628 (1995-10-01), None
patent: 8005703 (1996-01-01), None
patent: 92/11643 (1992-07-01), None
Betts. J., Patents Act 1977: Search Report Under Section 17 (5); Appl. No. GB9825959.1; Mar. 31, 1999, pp. 1-2.
Renault, S., International Search Report, App. No. PCT/EP99/08992, Apr. 14, 2000, pp. 1-5.

Affiliated with

Also associated with

Rating

Method of testing integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of testing integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of testing integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2913642