Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-10-01
2002-02-26
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
36
Reexamination Certificate
active
06350626
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of testing electromigration (EM) lifetime. More particularly, the present invention relates to a test methodology for fast wafer-level reliability (FWLR).
2. Description of Related Art
Reliability of metal interconnections become increasingly important with decreasing cross section area and increasing current density. EM (Electromigration) has been one of the most important reliability issues because it can cause open or short circuits in integrated circuit interconnects under normal operation conditions, resulting in circuit failure.
Conventional EM lifetime testing is performed in an oven at some elevated temperature with an adequately high current density passing through the test lines. In general, this kind of package-level testing can take weeks or even months to complete and hence it is difficult to provide fast feedback for new process development or routine monitor for statistical process control. As a result, fast EM tests performed at the wafer level are receiving great interest in industry. In addition, large current density and high temperature are employed in order to achieve the short testing time. The current density is in the order of 10 MA/cm
2
and temperature is higher than 300° C. Accordingly, a high amount of heat is generated and hence adds uncertainties and unintended effects to the EM tests.
Various WLR (Wafer-Level Reliability) EM tests have been proposed such as SWEAT(Standard Wafer-Level Electromigration Acceleration Test), BEM (Breakdown Energy of Metals), 1/f noise measurement and an isothermal test, in order to reduce the testing time and accurately control the heat. However, the conventional test techniques stated above fail to model EM lifetime in terms of microstructural characteristics of interconnects, such as line width and line temperature. It is important to model EM lifetime when attempting to understand and thus quantitatively describe the physical phenomena in various stressful conditions. Without modeling, WLR is difficult to develop or at its best can only be used as process monitor.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a method of testing EM lifetime, which can be used under different conditions of line width and temperatures. Thus, a high temperature, fast wafer-level reliability (FWLR) test is achieved.
This invention provides a full understanding of EM diffusion mechanism over a wide range of line widths and temperatures. Hence, this invention provides a method for testing the EM lifetime of a metal having a specific critical line width and a specific critical temperature under different conditions of line widths and temperatures.
The method of testing EM lifetime according to this invention comprises following steps. A pre-characterizing step is performed to obtain parameters comprising T
C
(critical temperature,), W
C
(critical line width), Q
GB
(activation energy of grain boundary diffusion) and Q
L
(the activation energy of lattice diffusion) of a metal prior to the use of the test methodology for a new technology. The pre-characterizing step is not necessary if the above parameters are known.
A t
50test
value is obtained by a WLR isothermal test at a relatively high temperature (T
test
), such as 400° C., which is higher than T
C
, can be implemented to reduce the test time to as little as a few seconds.
Whether a real line width (W) of the metal is narrower or wider than Wc is determined. For the wider line widths (i.e., W>W
C
), the diffusion mechanism can be dominated by either lattice diffusion (for T>T
C
) or grain boundary diffusion (for T<T
C
) which corresponds to two different activation energies (Q
L
and Q
GB
). The EM lifetime (t
50
) under normal operation condition (T
use
) can be obtained by conversion from T
test
to T
use
by using the equation (1a) and (1b).
For the narrower line widths,( i.e., W<W
C
), the diffusion mechanism is dominated by the lattice diffusion only and corresponds to single activation energy (Q
L
). The EM lifetime (t
50
) under normal operating condition (T
use
) can be directly obtained by conversion from T
test
to T
use
by using equation (2).
The equation (1a), (1c), and (2) is shown as follow:
When W>W
C
,
t
50
use
=
t
test
(
j
use
j
test
)
-
n
exp
(
Q
L
k
(
1
T
use
-
1
T
test
)
)
for
T
>
T
C
;
(1a)
t
50
use
=
t
test
(
j
use
j
test
)
-
n
exp
(
Q
GB
k
(
1
T
use
-
1
T
C
)
-
Q
L
kT
(
1
T
C
-
1
T
test
)
)
for
T
<
T
C
;
(1c)
When W≦W
C
,
t
50
use
=
t
test
(
j
use
j
test
)
-
n
exp
(
Q
L
k
(
1
T
use
-
1
T
test
)
)
(
2
)
t
test
and T
50use
represent the EM lifetime for testing temperature and a normal operation temperature, respectively. Q
GB
and Q
L
are the activation energies for grain boundary diffusion and lattice diffusion, respectively n is the constant which describes the current density j dependence and the fundamental physical arguments support n=2, and A is the proportionality constant which depends on the technology.
As embodied and broadly described herein, the metal can be Cu or Al. For example, the critical temperature of Al metal is about 390. For a 0.25 &mgr;m process, the critical line width is about 1 &mgr;m. The Q
L
and the Q
GB
of the Al metal are about 1.05 eV and 0.60 eV, respectively.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5760595 (1998-06-01), Edwards et al.
patent: 5801394 (1998-09-01), Isobe
patent: 6100101 (2000-08-01), Marathe et al.
patent: 6136619 (2000-10-01), Ceuninck et al.
Cheng Donald
Fu Kuan-Yu
Charles C. H. Wu & Associates
Fourson George
Garcia Joannie Adelle
United Microelectronics Corp.
Wu Charles C. H.
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