Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1999-05-26
2002-01-15
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000
Reexamination Certificate
active
06339389
ABSTRACT:
The present invention relates to a method of testing analog to digital converters (ADCs).
High speed ADCs are used in many varieties of applications; each application may require special consideration of one or more particular parameter. For example, designers of video (radar or TV) would pay particular attention to differential gain and phase, whereas designers using the ADC for radar would need to pay attention to aperture jitters. Other systems may need accurate information on analog power bandwidth or bit error rate. Specification requirements therefore differ from application to applications, and this can make comparisons of ADCs difficult. Therefore, it is important for both the design and system engineers to use special methods in order to evaluate the device's parameters. The evaluation methods falls into two categories. The first group utilises high speed Digital to Analog Converters (DACs) to reconstruct the digital output into an Analog form that can be displayed on an oscilloscope. The second group of methods looks directly at the digital data and uses DSP algorithms to analyse and extract all DC and AC errors.
Beat frequency testing is a quantitative test for ADC (Analog to Digital Converter) dynamic performance and may be used to quickly judge whether or not there are any gross problems with the ADC. In this technique, a full scale sinewave input signal is offset slightly in frequency from the ADC's sample rate. This frequency offset is selected such that on successive cycles of the input sinewave, the ADC output ideally would change by 1 LSB at the point of maximum slope (Slew rate's maximum point over one period of the input sinewave). Thus, the ADC sample point “walks” through the input signal as shown in FIG.
1
. When the data stored in memory is reconstructed using a low speed DAC (Digital to Analog Converter), the beat frequency, &Dgr;f is observed. Differential non linearities show up as horizontal lines in the observed beat frequency waveform and missing codes show up as gaps The large codes would appear as a widening of the differential codes appearing on the sinewave.
The envelope test is a variation of the beat frequency test in which the beat frequency &Dgr;f is selected such that the ADC output would be at the extreme ends of its range on successive cycles of the input sine wave. Like the beat frequency test, the envelope test is a qualitative test but is much more demanding on an ADC because it places a worst case slew condition on the unit's input. This condition represents the most stringent test of a converter's settling time.
In the beat frequency test, the samples “walk” through the input waveform, each output code ideally changing by 1 LSB. The offset frequency for a 1 LSB change on successive samples for an N bit ADC can be computed from the following (assuming a full scale input sinewave):
&Dgr;f=f
s
/2
N
&pgr;
Where &Dgr;f=Offset frequency
f
s
=Sampling Rate
f
s
+&Dgr;f=Input frequency
N=Number of Bits in the ADC
A known method of testing AID converters is to use a DAC as a reconstruction device and view the output response on a high speed, high resolution scope in order to verify linearity and dynamic parameters such as bandwidth, slew and distortion. This is normally performed by inputting a pure sinewave to the ADC under the test at nyquist and clock frequencies and observing the beat frequency generated.
This method has disadvantages, since it requires a high resolution DAC (higher than ADC by at least 2 bits) with a very low linearity error. It also requires use of external low pass filters to eliminate aliasing effects due to DAC. The time and effort required in identifying, constructing necessary boards and circuits is substantial. Additionally, the constructed analog output requires a high resolution, high speed analog scope with limited waveform manipulation such as data storage and data communication.
SUMMARY OF THE INVENTION
The purpose of this invention is to provide a method that reduces time and effort when evaluating high speed ADCs (especially integrated circuits) in the initial phases of design and development.
In a first aspect, the invention provides a method of analysing ADCs, comprising providing a test waveform, sampling the test waveform in an ADC at a frequency different from the test waveform, providing the output samples of the ADC to a logic analyser means, storing the output samples over a predetermined time interval in memory in the logic analyser means, and providing from the stored samples, a graphical visual representation of the sampled test waveform.
In a further aspect, the invention provides a system for analysing ADCs, comprising a source of a test waveform coupled to the input of an ADC, logic analyser means coupled to the output bus of the ADC, clock means for clocking the ADC at a frequency different from that of the test waveform, the logic analyser means including means for storing the output samples of the ADC, and including means for reconstructing from the stored samples, in visual graphical form, the test waveform sampled by the ADC.
In accordance with the invention, the visual representation of the test waveform, sampled at a beat frequency, may be observed and assessed to give rapidly information on various parameters of the ADC, as described below.
For the purposes of this specification, “logic analirser” means a device for accepting digital input samples on a parallel bus, storing the samples, and having means for displaying the stored samples in graphical form visually. A logic analyser is a well known tool used for trouble shooting digital circuits and debugging software problems. A personal computer may be used as a logic analyser, provided that suitable analysis software is loaded into the PC.
In this method, instead of using a DAC, an appropriate Logic Analyser with typical memory depth of around 4k or higher can be employed with graph (chart) reconstruction capability. When the analyser is set to the state analysis mode the output code can be viewed as a graph of states versus time. By conveniently adjusting the ADC input in real time the constructed waveform will represent each individual digital value into a time mapped sample value.
Beat frequencies generated will provide information on the dynamic behaviour of the ADC under the test. It must be noted that the beat frequency method if specifically useful when the display memory size is limited and device is operated at high input and clock frequencies. At these frequencies over sampling techniques depending on the display memory size would cause the state values to interleave hence making the analysis valueless.
This method eliminates the need for oscilloscope, DAC and Low pass filters and reduces parasitic artefact caused by extra interconnections and pcb's.
This invention allows fast evaluation of the Analog to Digital Converters at the different phases of the design and development. By examining the beat frequencies one can easily observe and identify the full power bandwidth, slew rate, distortion (flat spots), offset, comparator symmetries (flash types only) and other related parameters of interest for the ADC under test. Depending of the measurement results a designer quickly decide whether a full analysis using other methods such as DSP techniques is required or specific simulation and modification of the IC's circuitry is preferred.
REFERENCES:
patent: 4031462 (1977-06-01), Bouvier et al.
patent: 4763105 (1988-08-01), Jenq
patent: 4788492 (1988-11-01), Schubert
patent: 5159337 (1992-10-01), Lankreijer
patent: 5195530 (1993-03-01), Shindel
patent: 5361067 (1994-11-01), Pinckley
patent: 5712633 (1998-01-01), Bae
patent: 5774085 (1998-06-01), Yanagimoto et al.
patent: 5781138 (1998-07-01), Knudsen
patent: 5818370 (1998-10-01), Sooch et al.
patent: 5867410 (1999-02-01), Smallcombe et al.
patent: 5891041 (1999-04-01), Shinomura et al.
patent: 5914592 (1999-06-01), Saito
patent: 5995033 (1999-11-01), Roeckner et al.
patent: 6016113 (2000-01-01), Binder
LSI Logic Corporation
Mitchell Silberberg & Knup L.L.P.
Paik Steven S.
Tokar Michael
LandOfFree
Method of testing analog to digital converters does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of testing analog to digital converters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of testing analog to digital converters will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2852804