Method of testing an integrated circuit die, and an...

Details Method of testing an integrated circuit die, and an... Method of testing an integrated circuit die, and an...

2010-04-19

2010-12-14

Lee, Calvin (Department: 2892)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C257S203000

Reexamination Certificate

active

07851273

ABSTRACT:
In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

REFERENCES:
patent: 5641978 (1997-06-01), Jassowski
patent: 7728361 (2010-06-01), Zhang et al.

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