Method of testing an integrated circuit

Details Method of testing an integrated circuit Method of testing an integrated circuit

2000-09-14

2002-12-03

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S762010, C324S1540PB, C438S017000, C438S018000, C257S048000

Reexamination Certificate

active

06489800

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method and apparatus for testing an integrated circuit, and, more particularly, to a method of measuring absorbed current of an integrated circuit in a quiescent state and a related test circuit.
BACKGROUND OF THE INVENTION
Upon completion of the process to manufacture a plurality of identical integrated circuits on a wafer of semiconductor material, even before the individual devices are separated from one another, they are subjected to final testing on the wafer (final wafer test) by suitable automatic apparatus. The test comprises various programmed electrical measurements which are intended to ascertain whether each device conforms to certain functional requirements defined at the design stage. Devices which do not satisfy all of these requirements are identified after testing so that they can be rejected after the wafer has been divided up into chips, whilst the devices which have passed the test go on to subsequent assembly and encapsulation stages.
A parameter which is the subject of one of the most significant electrical measurements in the testing of digital or mixed analog and digital integrated circuits of large dimensions produced with the use of CMOS technology is the current at rest, in static conditions, that is, the current absorbed by the integrated circuit when it is connected to the supply but is functionally inactive and in a waiting condition (stand-by mode) or when the supply is deactivated (power-down mode). This parameter is commonly indicated IDDQ, where I indicates the current, DD indicates direct-current supply, and Q indicates the “quiescent” or rest state.
The IDDQ current measured is given basically by the sum of the so-called sub-threshold currents of the MOS transistors, including those which constitute the memory cells, and of the leakage currents due to manufacturing defects or material defects. Further leakage currents of the semiconductor junctions (junction leakage currents) are at least two orders of magnitude lower and are thus negligible. If the sample subjected to testing is defective in the sense which will be explained further below, the current measured also includes a contribution resulting directly from the defect.
For each integrated circuit subjected to testing, the IDDQ current measured is compared with a threshold value Ith, which is set beforehand by examining test samples of the same device and by taking into consideration suitable tolerance margins. If the comparison shows that the IDDQ value is equal to or greater than the value Ith, the device tested is identified for subsequent rejection.
The method of measuring the IDDQ current is recognized as being very important in programs for testing CMOS integrated circuits but becomes ever more difficult to perform as the complexity of the integrated circuits increases, that is, with increases in the density of integration and in the number of logic gates, which generally indicates the degree of complexity of a digital integrated circuit. To explain this fact further, it should be borne in mind that, with the refinement of integration techniques, there has been a change, within a short time, from IDDQ currents of between 1 &mgr;A and 10 &mgr;A for integrated circuits containing 1,000-10,000 logic gates produced by 1.5-1.0 &mgr;m technology to IDDQ currents of between 100 and 10,000 &mgr;A for integrated circuits containing 100,000-10 million logic gates produced by 0.5-0.2 &mgr;m technology.
It is known that the contribution of subthreshold currents to the IDDQ current increases in proportion to the number of transistors. On the other hand, the threshold current Ith must be set in a manner such that a defective device can be identified. That is, it must be equal to the sum of the IDDQ current measured for a good device and of a current smaller than the current If due to the presence even of a single electrical defect such as a short-circuit or a floating node in the integrated circuit. Since this current If is substantially independent of the complexity of the integrated circuit, the difference between the IDDQ current measured for a good device and the current Ith is smaller, as a percentage, the greater is the number of transistors in the integrated circuit. By way of example, if the IDDQ current for a device without electrical defects is 10 &mgr;A and if the current If due to a defect is at least 50 &mgr;A, the threshold current Ith may be fixed at 60 &mgr;A, that is, six times the IDDQ of a good device. If, however, the IDDQ of a good device is 1 mA, in order not to risk accepting as good those devices which have even a single defect contributing 50 &mgr;A to the IDDQ measurement, the threshold voltage Ith must be fixed at 1.05 mA, that is, at a value which differs from the IDDQ of a good device by only a fraction thereof ({fraction (1/20)} in this example). In conclusion, in the first case, the difference between IDDQ and Ith is 50 &mgr;A, which is 500% of the IDDQ current to be compared and, in the second case, the difference is still 50 &mgr;A, but this is only 5% of the IDDQ current to be compared. To ensure reliable results of the measurement even for devices with a high density of integration it is therefore necessary to use ever more sensitive and hence more complex detection circuits and ever more critical measurement methods.
To prevent this problem, it has been proposed to perform the IDDQ measurements by keeping the wafer containing the integrated circuits to be tested at a temperature much lower than ambient temperature, for example −40° C. In these conditions, the sub-threshold currents are reduced whilst the leakage currents due to defects of the structure increase (because of the increased mobility of the charge-carriers at low temperatures). Although this technique is effective, it is not applicable in practice in the mass production of integrated circuits because it requires extremely expensive apparatus designed to operate at low temperature.
SUMMARY OF THE INVENTION
The embodiments of the present invention are directed to a method of measuring the IDDQ current during the testing of integrated circuits with a high density of components which requires neither particularly sensitive detector circuits nor expensive apparatus.
This is achieved by the implementation of the method defined and characterized herein.
The method is directed to testing an integrated circuit having n-channel MOS transistors in p-type body regions and p-type MOS transistors in n-type body regions, and includes setting a current threshold value; supplying the integrated circuit in static conditions with a voltage supply having a positive pole and a negative pole; performing a biasing operation by applying to the p-type body regions a voltage potential that is negative relative to the negative pole of the supply and applying to the n-type body regions a voltage potential that is positive relative to the positive pole of the supply; measuring the current absorbed by the integrated circuit and comparing the current measured with the threshold value; and accepting the integrated circuit when the comparison shows that the current measured is less than the threshold value and rejecting the integrated circuit when the comparison shows that the current measured is greater than the threshold value.
In accordance with another aspect of the foregoing, the method includes setting the current threshold value that further comprises measuring the currents absorbed by a plurality of integrated circuits of the same type as those to be tested, supplied in static conditions and subjected to the above-mentioned biasing operation; and performing a statistical analysis of the results of the measurement.
In accordance with another aspect of the present invention, an integrated circuit is provided that includes a plurality of n-channel MOS transistors having source regions connected to a first common conductive strip, p-type body regions containing the n-channel MOS transistors and connected to a second common conductive strip, p-channel MOS transistors ha

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