Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-01-29
2004-08-10
Zarneke, David. A. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C257S048000, C438S015000, C324S1540PB, C439S912000
Reexamination Certificate
active
06774659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packaging, and more particularly to semiconductor package devices and their methods of manufacture and testing.
2. Description of the Related Art
In the field of electronic systems, there is a continuous need to increase performance and reduce size. This is largely achieved by improving semiconductor wafer manufacturing and semiconductor packaging technologies. Wafer manufacturing involves simultaneously fabricating numerous semiconductor chips as a batch on a silicon wafer using various etching, doping and depositing steps. After the wafer is complete, the chips are separated from one another and packaged.
Wafer manufacturing strives to reduce transistor or capacitor feature size in order to increase circuit density and enhance functionality. Device geometries with sub-micron line widths are so common that individual chips routinely contain millions of electronic devices. Reduced feature size has been quite successful in improving electronic systems, and continuous development is expected in the future. However, significant obstacles to further reduction in feature size are being encountered. These obstacles include defect density control, optical system resolution limits, and availability of processing material and equipment. Attention has therefore increasingly shifted to semiconductor packaging as a means to fulfill the relentless demands for enhanced system performance.
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. Traditionally, a single chip is individually housed in a single-chip package that is connected to other single-chip packages through a printed circuit board (or motherboard) which supplies power to the chips and provides signal routing among the chips. The single-chip package has connection media that is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate).
Several connection techniques are widely used for connecting the chip pads and the connection media. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding. Wire bonding is by far the most common. In this approach, wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. TAB requires mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface. Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Many variations exist on these basic methods.
A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuitry, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used. While flip-chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. An adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. The solder joints exhibit increased electrical resistance as well as cracks and voids over time due to fatigue from thermo-mechanical stresses. Further, the solder is typically a tin-lead alloy and lead-based materials are becoming far less popular due to environmental concerns over disposing of toxic materials and leaching of toxic materials into ground water supplies. Thus, none of these conventional connection techniques are entirely satisfactory.
Conventional single-chip packages typically have an area (or footprint) that is many times larger than the area of the chip, causing the printed circuit board to have excessively large area relative to the chips. However, as chip speeds increase, it becomes critical to position the chips close together since excessive signal transmission distance deteriorates signal integrity and propagation times. Other considerations such as manufacturing cost, reliability, heat transfer, moisture resistance, mounting and interconnect standardization, testability, and quality control have also become focal points of chip packaging.
Single-chip packages such as thin small outline packages (TSOPs) and ball grid arrays (BGAs) have been developed to address these considerations. TSOPs include an insulative housing that encapsulates the chip and rows of leads that protrude from opposing side surfaces of the insulative housing and are bent to provide distal end portions that are coplanar with or extend below the bottom surface of the insulative housing. The leads are connected to the chip pads in one-to-one relation. BGAs include a substrate with a top surface upon which the chip is mounted, an insulative housing that encapsulates the chip, and an array of balls that protrude from the bottom surface of the substrate. The balls are connected to the chip pads in one-to-one relation.
TSOPs and BGAs provide certain advantages but they have disadvantages as well. For instance, TSOPs are fairly compact but the leads can require significantly larger area than the chip. Thus, TSOPs tend to occupy more surface area than BGAs. BGAs, on the other hand, can be more difficult to test than TSOPs since the balls are less easily inserted into and removed from a test socket than are TSOP leads. Furthermore, standard TSOP test sockets are readily available, whereas the balls are often configured to match the electrical contact arrangement on the printed circuit board in the next level assembly. As a result, a customized test socket may be needed to match the balls. Moreover, TSOP and BGA packages often employ wire bonding, TAB or flip-chip bonding, and as mentioned above, none of these chip pad connection techniques are entirely satisfactory.
In view of the various development stages and limitations in currently available semiconductor package devices, there is a need for a semiconductor package device that is cost-effective, reliable, manufacturable, provides excellent mechanical and electrical performance, and is flexible enough to accommodate test sockets and printed circuit boards with different contact terminal arrangements.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor package device that provides a low cost, high performance, high reliability package. Another object of the present invention is to provide a convenient, cost-effective method of making a semiconductor package device. Still another object of the present invention is to provide a method of testing a semiconductor package device.
Generally speaking, the present invention provides a semiconductor package device with terminals that protrude downwardly from the bottom surface of an insulative housing and leads that protrude laterally from the side surfaces of the insulative housing. The terminals and leads are connected together and to the chip pads in one-to-one relation. As a result, the leads can be inserted into a test socket that need not contact the terminals, and the terminals can be mounted on a printed circuit board that need not contact the leads.
In accordance with
Bridge Semiconductor Corporation
Patel Paresh
Sigmond David M.
Zarneke David. A.
LandOfFree
Method of testing a semiconductor package device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of testing a semiconductor package device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of testing a semiconductor package device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298733