Method of target generation for multilevel hierarchical circuit

Details Method of target generation for multilevel hierarchical circuit Method of target generation for multilevel hierarchical circuit

1994-04-12

1995-12-12

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054756073

ABSTRACT:
Generating delay targets for creating a multilevel hierarchical circuit design by providing a hierarchical design description and delay constraints of the circuit design; generating a net measure for each net and macro cell of the circuit design, and generating an abstract delay model for each macro cell of the circuit design based on the design description, wherein net measure is the estimated resistive-capacitive delay of a net derived from the estimated length of the net based on area-driven design, and an abstract delay model is a description of delays through a macro cell; generating delay targets for the nets and macro cells based on the net measures, the abstract delay models and the delay constraints; and creating the circuit design based on the delay targets.

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