Method of synchronizing read timing in a high speed memory...

Details Method of synchronizing read timing in a high speed memory... Method of synchronizing read timing in a high speed memory...

2005-01-25

2005-01-25

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189040

Reexamination Certificate

active

06847583

ABSTRACT:
The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

REFERENCES:
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patent: 6125078 (2000-09-01), Ooishi et al.
patent: 6587913 (2003-07-01), Campanale et al.

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