Boots – shoes – and leggings
Patent
1982-03-19
1984-11-06
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1300
Patent
active
044815760
ABSTRACT:
When addressing a store comprising a plurality of low speed memory blocks each of which can be accessed through a high speed buffer having a limited number of memory elements, in accordance with a pattern which is more flexible than sequential then conflicts can occur due to overloading of the memory elements. In order to avoid this, prior to storing data, the address parameters are calculated taking into account the read/write sequence, depth of buffer and access times and a check is made to see if there are any conflicts among the simulated addresses. If so then a number of alternative measures can be tried in order to resolve the conflicts. Such measures include the use of a small capacity, high speed vestigial memory, adding an offset to the addresses or skipping a number of addresses. Once acceptable address parameters have been calculated then a hardware address generator can be instructed to address data accordingly.
REFERENCES:
patent: 4383296 (1983-05-01), Sander
Briody Thomas A.
Cannon, Jr. James J.
Haken Jack E.
U.S. Philips Corporation
Zache Raulfe B.
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