Method of state determination in lock-stepped processors

Details Method of state determination in lock-stepped processors Method of state determination in lock-stepped processors

1993-07-06

1995-07-18

Beausoliel, Jr., Robert W.

Excavating

371 12, 3642688, 3642632, 364DIG1, G06F 1100

Patent

active

054350018

ABSTRACT:
A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip. The maintenance diagnostic chip includes logic to halt either of the microprocessors if an error is detected, and read out the state of the microprocessors and a secondary cache attached to the microprocessors, before the state of the microprocessors at the time of the fault changes to a different state which might hide evidence of the cause of the fault.

REFERENCES:
patent: 4528629 (1985-07-01), Breitling
patent: 5269006 (1993-12-01), Dohse et al.
patent: 5276823 (1994-01-01), Cutts, Jr. et al.
patent: 5295258 (1994-03-01), Jewett et al.

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